🐛 Fix dynamic handling of top-level interrupt initialization#937
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Problem: - The cached state of IRQs which are statically enabled is not properly initialized. Solution: - For IRQs which have been statically enabled, make sure the cached register state is also set to enabled.
Problem: - Interrupt register values are "cached", but it isn't really a cache: it's written through immediately and serves to avoid RMW. "Cache" implies things that don't occur; a better way to describe this is a shadow value. Solution: - Rename `cached_*` to `shadow_*` for the dynamic interrupt manager.
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mjcaisse-intel
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Problem:
initialized.
Solution:
state is also set to enabled.