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Releases: intel/multi_power_sequencer
Releases · intel/multi_power_sequencer
Release list
v3.0.0
v3.0.0 Features added:
- Added Non-volatile error logging, black box data log, and timestamp from TOD clock
- Added support for non-PMBus* control plane interfaces with "Alignment Bridge"
- Added page support for all rails, including digital rails
- Added undervoltage error logging on digital POK inputs
- Added logging for qualification window timeout errors
- Added new "Sequencer Monitor" component, which combines the "Sequencer Decoder" and
"Sequencer Voltage Monitor" to a single component for simpler configuration. - Added System Console script with numerous status and control functions, which can
be used to easily interface to the sequencer over JTAG and the Alignment Bridge. - Changed the Sequencer Decoder to allow zero ADC interfaces, for a fully digital
implementation (with PMBus support or logging).
v2.2.0
v2.2.0 Features added:
- Added PLL reset
- Updated reset architecture in reference design by adding power-on reset and sequencing.
- Provided option for open-drain or push-pull drivers on nFAULT, VRAIL_ENA, and VRAIL_DCHG