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realtek: pci: add rtl9607 pcie controller support#5

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jameywine wants to merge 1 commit intortl9607c-devfrom
rtl9607c-dev-pci
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realtek: pci: add rtl9607 pcie controller support#5
jameywine wants to merge 1 commit intortl9607c-devfrom
rtl9607c-dev-pci

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@jameywine
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This commit adds support for PCIE controller on RTL9607C / RTL8198D.

RTL9607C / RTL8198D has 2 PCIE ports for 2 wifi chipsets.

It also comes with pcie phy driver companion which initializes phy and other misc stuff like ip controller using syscon nodes. Since it is very similar in the way phy writes are done in rtk usb3 phy driver, most of the structure was copied over to the pcie phy driver.

This pull request is just here so that people can test and see and discuss about it, as it is not really for merging to rtl9607c-dev_gpio branch.

Big thanks to naseef's work on pci as it allowed me to build upon it and make it more upstream friendly.

Hey @naseef , if you can, could you test it out on your end as well?

Comment thread target/linux/realtek/dts/rtl9607_bt-pon_bt-g711ax.dts
@jameywine
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Applied suggested changes to move pinmux node to the board device tree.

I have also made some cleanups to pcie and phy drivers

  • Made use of reset controller in pcie phy just like in the usb branch
  • removed the assert/deassert gpio functions from pcie controller driver in favor of directly using gpiod_set_value_cansleep. It shouldn't cause issues because gpio get function is optional and thus returns null instead of error.
  • various error text changes

@jameywine
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forgot to add reset properties to the pcie phy nodes in my previous push. That should be fixed now.

Comment thread target/linux/realtek/files-6.12/drivers/pci/controller/pcie-realtek.c Outdated
Comment thread target/linux/realtek/files-6.12/drivers/pci/controller/pcie-realtek.c Outdated
Comment thread target/linux/realtek/files-6.12/drivers/phy/realtek/phy-rtk-pcie.c Outdated
Comment thread target/linux/realtek/files-6.12/drivers/phy/realtek/phy-rtk-pcie.c Outdated
@ProMix0
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ProMix0 commented Mar 5, 2026

Can't find SoC revision checking... I'll need to test it on rev. A

@jameywine
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jameywine commented Mar 5, 2026 via email

@ProMix0
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ProMix0 commented Mar 5, 2026

Tested the driver. Of course, it don't work with rev. A (but works with rev. C)

@jameywine
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jameywine commented Mar 6, 2026 via email

@jameywine
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added revA compatibles to the phy pcie driver, that should make pcie ports on RTL9607C rev A work..

Comment thread target/linux/realtek/files-6.12/drivers/phy/realtek/phy-rtk-pcie.c
if (!rtk_phy->phy_cfg)
return dev_err_probe(dev, -ENOMEM, "Failed to allocate phy_cfg\n");;

memcpy(rtk_phy->phy_cfg, phy_cfg, sizeof(*phy_cfg));
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Why not referencing shared const struct?

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That is just how the phy-rtk-usb3 code had done it and i copied that

@ProMix0
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ProMix0 commented Mar 6, 2026

PCI on revA failing to bring link up, which indicating improper PHY initialization. Actual revision works fine

@jameywine
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which indicating improper PHY initialization.

just noticed that i have forgotten to change the numbers in the square brackets after copying some of the rows

		    [15] = {0x0f, 0x000c},
		    [15] = {0x1b, 0xaea1},
		    [15] = {0x1e, 0x28eb},
		    ....
		    [39] = {0x27, 0x011a},
		    [39] = {0x2f, 0x65bd}, },

will fix it right away

@jameywine
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@ProMix0 hey,
I would like to know, when you can test pcie again on rtl9607c rev a? I am currently trying to do last minute checks before sending patches upstream as we should be pretty much done with usb and pcie drivers

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ProMix0 commented Mar 24, 2026

Seems to work now. I'll check again later

RevA bootlog (PCI part)

Details
[    1.066756] pinctrl-single 1b000038.pinmux: 96 pins, size 12
[    1.268331] realtek-pcie 18b20000.pcie: host bridge /pcie@18b20000 ranges:
[    1.276164] realtek-pcie 18b20000.pcie:      MEM 0x001a000000..0x001affffff -> 0x001a000000
[    1.285631] realtek-pcie 18b20000.pcie:       IO 0x0018e00000..0x0018e0ffff -> 0x0000000000
[    1.295878] realtek-pcie 18b00000.pcie: host bridge /pcie@18b00000 ranges:
[    1.303798] realtek-pcie 18b00000.pcie:      MEM 0x0019000000..0x0019ffffff -> 0x0019000000
[    1.313219] realtek-pcie 18b00000.pcie:       IO 0x0018c00000..0x0018c0ffff -> 0x0000000000
[    1.323985] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[    1.335333] printk: legacy console [ttyS0] disabled
[    1.341566] 18002000.uart: ttyS0 at MMIO 0x18002000 (irq = 24, base_baud = 12500000) is a 16550A
[    1.351558] printk: legacy console [ttyS0] enabled
[    1.351558] printk: legacy console [ttyS0] enabled
[    1.362276] printk: legacy bootconsole [early0] disabled
[    1.362276] printk: legacy bootconsole [early0] disabled
[    1.374839] printk: legacy bootconsole [ns16550a0] disabled
[    1.374839] printk: legacy bootconsole [ns16550a0] disabled
[    1.415764] brd: module loaded
[    1.421800] spi-nand spi0.0: GigaDevice SPI NAND was found.
[    1.428164] spi-nand spi0.0: 128 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
[    1.437720] 5 fixed-partitions partitions found on MTD device spi0.0
[    1.444962] Creating 5 MTD partitions on "spi0.0":
[    1.450392] 0x000000000000-0x0000000e0000 : "u-boot"
[    1.457880] 0x0000000e0000-0x000000100000 : "u-boot-env"
[    1.465191] 0x000000100000-0x000000120000 : "u-boot-env2"
[    1.473495] 0x000000120000-0x000000140000 : "static_conf"
[    1.480705] 0x000000140000-0x000007d80000 : "ubi"
[    1.604428] i2c_dev: i2c /dev entries driver
[    1.620737] NET: Registered PF_INET6 protocol family
[    1.630060] Segment Routing with IPv6
[    1.634252] In-situ OAM (IOAM) with IPv6
[    1.638886] NET: Registered PF_PACKET protocol family
[    1.644581] 8021q: 802.1Q VLAN Support v1.8
[    1.685538] realtek-pcie 18b20000.pcie: host bridge /pcie@18b20000 ranges:
[    1.693460] realtek-pcie 18b20000.pcie:      MEM 0x001a000000..0x001affffff -> 0x001a000000
[    1.702880] realtek-pcie 18b20000.pcie:       IO 0x0018e00000..0x0018e0ffff -> 0x0000000000
[    1.930675] realtek-pcie 18b20000.pcie: link up, 5.0 GT/s PCIe
[    1.937555] realtek-pcie 18b20000.pcie: PCI host bridge to bus 0000:00
[    1.944887] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.951031] pci_bus 0000:00: root bus resource [mem 0x1a000000-0x1affffff]
[    1.958719] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.965664] pci 0000:00:00.0: [10ec:8196] type 01 class 0x060400 PCIe Root Port
[    1.973870] pci 0000:00:00.0: PCI bridge to [bus 00]
[    1.979443] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
[    1.986241] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
[    1.993836] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff pref]
[    2.001977] pci 0000:00:00.0: supports D1
[    2.006454] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    2.013274] pci 0000:00:01.0: [10ec:b814] type 00 class 0x028000 PCIe Endpoint
[    2.021425] pci 0000:00:01.0: BAR 0 [io  0x1000-0x10ff]
[    2.027288] pci 0000:00:01.0: BAR 2 [mem 0x1a200000-0x1a20ffff 64bit]
[    2.034620] pci 0000:00:01.0: supports D1 D2
[    2.039399] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    2.047893] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.057271] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    2.063175] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[    2.070604] pci 0000:00:00.0: bridge window [mem 0x1a000000-0x1a0fffff]: assigned
[    2.078984] pci 0000:00:00.0: bridge window [mem 0x1a100000-0x1a1fffff pref]: assigned
[    2.087820] pci 0000:00:01.0: BAR 2 [mem 0x1a200000-0x1a20ffff 64bit]: assigned
[    2.096029] pci 0000:00:00.0: bridge window [io  0x0000-0x0fff]: assigned
[    2.103626] pci 0000:00:01.0: BAR 0 [io  0x1000-0x10ff]: assigned
[    2.110459] pci 0000:00:00.0: PCI bridge to [bus 01]
[    2.115998] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
[    2.122814] pci 0000:00:00.0:   bridge window [mem 0x1a000000-0x1a0fffff]
[    2.130407] pci 0000:00:00.0:   bridge window [mem 0x1a100000-0x1a1fffff pref]
[    2.138482] pci_bus 0000:00: resource 4 [mem 0x1a000000-0x1affffff]
[    2.145476] pci_bus 0000:00: resource 5 [io  0x0000-0xffff]
[    2.151719] pci_bus 0000:01: resource 0 [io  0x0000-0x0fff]
[    2.157967] pci_bus 0000:01: resource 1 [mem 0x1a000000-0x1a0fffff]
[    2.164968] pci_bus 0000:01: resource 2 [mem 0x1a100000-0x1a1fffff pref]
[    2.173328] realtek-pcie 18b00000.pcie: host bridge /pcie@18b00000 ranges:
[    2.181155] realtek-pcie 18b00000.pcie:      MEM 0x0019000000..0x0019ffffff -> 0x0019000000
[    2.190558] realtek-pcie 18b00000.pcie:       IO 0x0018c00000..0x0018c0ffff -> 0x0000000000
[    2.398964] realtek-pcie 18b00000.pcie: link up, 2.5 GT/s PCIe
[    2.405750] realtek-pcie 18b00000.pcie: PCI host bridge to bus 0001:00
[    2.413092] pci_bus 0001:00: root bus resource [bus 00-ff]
[    2.419269] pci_bus 0001:00: root bus resource [mem 0x19000000-0x19ffffff]
[    2.426988] pci 0001:00:00.0: [10ec:8196] type 01 class 0x060400 PCIe Root Port
[    2.435200] pci 0001:00:00.0: PCI bridge to [bus 00]
[    2.440788] pci 0001:00:00.0:   bridge window [io  0x0000-0x0fff]
[    2.447591] pci 0001:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
[    2.455177] pci 0001:00:00.0:   bridge window [mem 0x00000000-0x000fffff pref]
[    2.463320] pci 0001:00:00.0: supports D1
[    2.467794] pci 0001:00:00.0: PME# supported from D0 D1 D3hot
[    2.474555] pci 0001:00:01.0: [10ec:818c] type 00 class 0x028000 PCIe Endpoint
[    2.482708] pci 0001:00:01.0: BAR 0 [io  0x0000-0x00ff]
[    2.488598] pci 0001:00:01.0: BAR 2 [mem 0x00000000-0x0000ffff 64bit]
[    2.496002] pci 0001:00:01.0: supports D1 D2
[    2.500794] pci 0001:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    2.509294] pci 0001:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.518591] pci 0001:00:00.0: PCI bridge to [bus 01-ff]
[    2.524454] pci_bus 0001:01: busn_res: [bus 01-ff] end is updated to 01
[    2.531927] pci 0001:00:00.0: bridge window [mem 0x19000000-0x190fffff]: assigned
[    2.540333] pci 0001:00:00.0: bridge window [mem 0x19100000-0x191fffff pref]: assigned
[    2.549193] pci 0001:00:01.0: BAR 2 [mem 0x19200000-0x1920ffff 64bit]: assigned
[    2.557366] pci 0001:00:00.0: bridge window [io  size 0x1000]: can't assign; no space
[    2.566130] pci 0001:00:00.0: bridge window [io  size 0x1000]: failed to assign
[    2.574299] pci 0001:00:01.0: BAR 0 [io  size 0x0100]: can't assign; no space
[    2.582275] pci 0001:00:01.0: BAR 0 [io  size 0x0100]: failed to assign
[    2.589683] pci 0001:00:00.0: PCI bridge to [bus 01]
[    2.595222] pci 0001:00:00.0:   bridge window [mem 0x19000000-0x190fffff]
[    2.602809] pci 0001:00:00.0:   bridge window [mem 0x19100000-0x191fffff pref]
[    2.610882] pci_bus 0001:00: Some PCI device resources are unassigned, try booting with pci=realloc
[    2.620995] pci_bus 0001:00: resource 4 [mem 0x19000000-0x19ffffff]
[    2.628008] pci_bus 0001:01: resource 1 [mem 0x19000000-0x190fffff]
[    2.635002] pci_bus 0001:01: resource 2 [mem 0x19100000-0x191fffff pref]

P.S. There is problem with BAR assignment on port1 (on both revisions). I guess, that's what FL_SET_BAR in SDK for

@ProMix0
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ProMix0 commented Mar 25, 2026

On the other day PCI works, it's good. But tests from anyone with revA are appreciated

Also replaced memcpy with static const reference since it simpler. Would like to replace this static buffers for PHY parameters int phy_cfg to spare some space (a few dozens, maybe hundred of bytes), but config definitions will look worse (in my taste)

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jameywine commented Mar 25, 2026 via email

@naseef
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naseef commented Mar 25, 2026

But tests from anyone with Reva are appreciated
You could send a message to naseef as they also have revA chip Maybe through OpenWrt forum though as they didn't seem to see/reply to my mention in the pull request message

I am watching this thread , I would like to test, but the main blocker for me is both the Wifi radio drivers are not supported by any of the Realtek wireless drivers . Earlier I was modfying compatible, but I am not sure it is 100% compatible since there were so many dmesg error outputs

What about your devices? Do they have the wifi radio drivers?

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jameywine commented Mar 25, 2026 via email

@ProMix0
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ProMix0 commented Mar 26, 2026

but the main blocker for me is both the Wifi radio drivers are not supported

Yes, it doesn't allow proper PCIe testing, but for now we could test if everything before link up works. Main question right now - do you also have port 0 with PCIe 2.0?

@jameywine jameywine force-pushed the rtl9607c-dev branch 2 times, most recently from 542fe8d to 606fbc3 Compare March 29, 2026 17:49
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There is rtw89 driver present though and while rtl8832br and rtl8192xbr are not supposed, I am now curious to just add an entry to pci_device_id stuct in the rtw8851be.c file for 0xb832 and I see if it works at all.

So i did that, but i can't tell why rtw89 doesn't build even though i have enabled the respective configs

+CONFIG_RTW89=y
+CONFIG_RTW89_8852B=y
+CONFIG_RTW89_8852B_COMMON=y
+CONFIG_RTW89_8852BE=y
+CONFIG_RTW89_CORE=y
+CONFIG_RTW89_DEBUG=y
+CONFIG_RTW89_DEBUGMSG=y
...
+CONFIG_WLAN=y
+CONFIG_WLAN_VENDOR_REALTEK=y

something must be wrong with my setup...

and yeah, here is the patch

--- a/drivers/net/wireless/realtek/rtw89/rtw8852be.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852be.c
@@ -87,6 +87,10 @@ static const struct pci_device_id rtw89_
 		PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb85b),
 		.driver_data = (kernel_ulong_t)&rtw89_8852be_info,
 	},
+	{
+		PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb832),
+		.driver_data = (kernel_ulong_t)&rtw89_8852be_info,
+	}
 	{},
 };
 MODULE_DEVICE_TABLE(pci, rtw89_8852be_id_table);

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@ProMix0 hey
if you have time, could you maybe check on why rtw89 driver wouldn't build and maybe do an attempt yourself?
Cause that is the only roadblock for me personally before i want to send it upstream for reviews. I want to make sure that the rtw89 with that patch above does something at the very least.

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ProMix0 commented Apr 6, 2026

I think we shouldn't hurry with sending to upstream. For example, there is issues with pcie1 BAR. Personally I would prefer to send solid tested and working driver rather than driver that just... loads, you know

No luck with rtw89 - no one firmware doesn't run smoothly. Tried to copy from my system - didn't go. Firmware from reference loads, but there are error while interacting with fw, but it should be solvable (you could move any fw .bin from g6_wifi_driver/phl/hal_g6/mac/fw_ax/rtl8852c/ to target/linux/realtek/base-files/lib/firmware/rtw89/rtw8852b_fw-1.bin)

Details
[    1.573266] realtek-pcie 18b20000.pcie: host bridge /pcie@18b20000 ranges:
[    1.581112] realtek-pcie 18b20000.pcie:      MEM 0x001a000000..0x001affffff -> 0x001a000000
[    1.590502] realtek-pcie 18b20000.pcie:       IO 0x0018e00000..0x0018e0ffff -> 0x0000000000
[    1.826487] realtek-pcie 18b20000.pcie: link up, 5.0 GT/s PCIe
[    1.833295] realtek-pcie 18b20000.pcie: PCI host bridge to bus 0000:00
[    1.840675] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.846859] pci_bus 0000:00: root bus resource [mem 0x1a000000-0x1affffff]
[    1.854531] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.861518] pci 0000:00:00.0: [10ec:8196] type 01 class 0x060400 PCIe Root Port
[    1.869736] pci 0000:00:00.0: PCI bridge to [bus 00]
[    1.875326] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
[    1.882135] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
[    1.889750] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff pref]
[    1.897918] pci 0000:00:00.0: supports D1
[    1.902401] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    1.909145] pci 0000:00:01.0: [10ec:b832] type 00 class 0x028000 PCIe Endpoint
[    1.917293] pci 0000:00:01.0: BAR 0 [io  0x0000-0x00ff]
[    1.923147] pci 0000:00:01.0: BAR 2 [mem 0x00000000-0x000fffff 64bit]
[    1.930474] pci 0000:00:01.0: supports D1 D2
[    1.935284] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    1.943659] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    1.952860] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    1.958777] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[    1.966245] pci 0000:00:00.0: bridge window [mem 0x1a000000-0x1a0fffff]: assigned
[    1.974598] pci 0000:00:00.0: bridge window [mem 0x1a100000-0x1a1fffff pref]: assigned
[    1.983478] pci 0000:00:01.0: BAR 2 [mem 0x1a200000-0x1a2fffff 64bit]: assigned
[    1.991691] pci 0000:00:00.0: bridge window [io  0x0000-0x0fff]: assigned
[    1.999321] pci 0000:00:01.0: BAR 0 [io  0x1000-0x10ff]: assigned
[    2.006174] pci 0000:00:00.0: PCI bridge to [bus 01]
[    2.011717] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
[    2.018557] pci 0000:00:00.0:   bridge window [mem 0x1a000000-0x1a0fffff]
[    2.026172] pci 0000:00:00.0:   bridge window [mem 0x1a100000-0x1a1fffff pref]
[    2.034229] pci_bus 0000:00: resource 4 [mem 0x1a000000-0x1affffff]
[    2.041268] pci_bus 0000:00: resource 5 [io  0x0000-0xffff]
[    2.047529] pci_bus 0000:01: resource 0 [io  0x0000-0x0fff]
[    2.053743] pci_bus 0000:01: resource 1 [mem 0x1a000000-0x1a0fffff]
[    2.060772] pci_bus 0000:01: resource 2 [mem 0x1a100000-0x1a1fffff pref]
[    2.069713] pcieport 0000:00:00.0: AER: enabled with IRQ 27
[    2.079524] rtw89_8852be 0000:00:01.0: loaded firmware rtw89/rtw8852b_fw-1.bin
[    2.089671] rtw89_8852be 0000:00:01.0: enabling device (0000 -> 0003)
[    2.118908] rtw89_8852be 0000:00:01.0: Firmware version 0.27.54.0 (145b188d), cmd version 0, type 1
[    2.131191] rtw89_8852be 0000:00:01.0: [ERR]MDIO R16 0x1B fail ret=-145!
[    2.140712] rtw89_8852be 0000:00:01.0: [ERR]MDIO R16 0x1D fail ret=-145!
[    2.148356] rtw89_8852be 0000:00:01.0: [ERR] pcie autok_x fail -145
[    2.157160] rtw89_8852be 0000:00:01.0: failed to setup chip information
[    2.166083] rtw89_8852be 0000:00:01.0: probe with driver rtw89_8852be failed with error -145
[    2.176156] realtek-pcie 18b00000.pcie: host bridge /pcie@18b00000 ranges:
[    2.183867] realtek-pcie 18b00000.pcie:      MEM 0x0019000000..0x0019ffffff -> 0x0019000000
[    2.193282] realtek-pcie 18b00000.pcie:       IO 0x0018c00000..0x0018c0ffff -> 0x0000000000
[    2.416026] realtek-pcie 18b00000.pcie: link up, 2.5 GT/s PCIe
[    2.422756] realtek-pcie 18b00000.pcie: PCI host bridge to bus 0001:00
[    2.430124] pci_bus 0001:00: root bus resource [bus 00-ff]
[    2.436292] pci_bus 0001:00: root bus resource [mem 0x19000000-0x19ffffff]
[    2.444012] pci 0001:00:00.0: [10ec:8196] type 01 class 0x060400 PCIe Root Port
[    2.452194] pci 0001:00:00.0: PCI bridge to [bus 00]
[    2.457760] pci 0001:00:00.0:   bridge window [io  0x0000-0x0fff]
[    2.464555] pci 0001:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
[    2.472145] pci 0001:00:00.0:   bridge window [mem 0x00000000-0x000fffff pref]
[    2.480273] pci 0001:00:00.0: supports D1
[    2.484741] pci 0001:00:00.0: PME# supported from D0 D1 D3hot
[    2.491470] pci 0001:00:01.0: [10ec:0192] type 00 class 0x028000 PCIe Endpoint
[    2.499591] pci 0001:00:01.0: BAR 0 [io  0x0000-0x00ff]
[    2.505464] pci 0001:00:01.0: BAR 2 [mem 0x00000000-0x000fffff 64bit]
[    2.512795] pci 0001:00:01.0: supports D1 D2
[    2.517571] pci 0001:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    2.525945] pci 0001:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.535281] pci 0001:00:00.0: PCI bridge to [bus 01-ff]
[    2.541201] pci_bus 0001:01: busn_res: [bus 01-ff] end is updated to 01
[    2.548678] pci 0001:00:00.0: bridge window [mem 0x19000000-0x190fffff]: assigned
[    2.557070] pci 0001:00:00.0: bridge window [mem 0x19100000-0x191fffff pref]: assigned
[    2.565931] pci 0001:00:01.0: BAR 2 [mem 0x19200000-0x192fffff 64bit]: assigned
[    2.574100] pci 0001:00:00.0: bridge window [io  size 0x1000]: can't assign; no space
[    2.582854] pci 0001:00:00.0: bridge window [io  size 0x1000]: failed to assign
[    2.591031] pci 0001:00:01.0: BAR 0 [io  size 0x0100]: can't assign; no space
[    2.599013] pci 0001:00:01.0: BAR 0 [io  size 0x0100]: failed to assign
[    2.606414] pci 0001:00:00.0: PCI bridge to [bus 01]
[    2.611948] pci 0001:00:00.0:   bridge window [mem 0x19000000-0x190fffff]
[    2.619537] pci 0001:00:00.0:   bridge window [mem 0x19100000-0x191fffff pref]
[    2.627617] pci_bus 0001:00: Some PCI device resources are unassigned, try booting with pci=realloc
[    2.637731] pci_bus 0001:00: resource 4 [mem 0x19000000-0x19ffffff]
[    2.644716] pci_bus 0001:01: resource 1 [mem 0x19000000-0x190fffff]
[    2.651718] pci_bus 0001:01: resource 2 [mem 0x19100000-0x191fffff pref]
[    2.660832] pcieport 0001:00:00.0: AER: enabled with IRQ 28

Pushed config for rtw89 here

@jameywine
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For example, there is issues with pcie1 BAR

Could it be related to the same issue as in econet pcie? Looks similar https://lore.kernel.org/linux-pci/20260312165332.569772-4-cjd@cjdns.fr/#t

@ProMix0
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ProMix0 commented Apr 6, 2026

Maybe, but I've applied patch, and it didn't help. Same bootlog

This commit adds support for PCIE controller on RTL9607C / RTL8198D.

RTL9607C / RTL8198D has 2 PCIE ports for 2 wifi chipsets.

It also comes with pcie phy driver companion which initializes phy and
other misc stuff like ip controller using syscon nodes. Since it is very
similar in the way phy writes are done in rtk usb3 phy driver, most of the
structure was copied over to the pcie phy driver.

Signed-off-by: Rustam Adilov <adilov@tutamail.com>
@naseef
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naseef commented Apr 9, 2026

@jameywine can we try mailing the rtw88 maintainers through mailing list ( seems like they are from realtek team itself) on supporting the wifi in our devices at least? we would need the wifi drivers anyway down the road

@jameywine
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jameywine commented Apr 9, 2026 via email

@jameywine
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no one firmware doesn't run smoothly

Have you tried loading the firmware from this directory? it appears they are for both rtl8192xb and rtl8832br by the presence of #if defined(MAC_8192XB_SUPPORT) || defined(MAC_8832BR_SUPPORT).

there is issues with pcie1 BAR

given that, the ->flags variable doesn't change anywhere in the vendor pci driver from its default FL_MDIO_RESET, it has to be impossible for the register writes to happen under if (p->flags & FL_SET_BAR) { statement.

Something i also want to do is to see what is behind the pci debug messages because only today have i noticed that there is config PCI_DEBUG.

config PCI_DEBUG
	bool "PCI Debugging"
	depends on DEBUG_KERNEL
	help
	  Say Y here if you want the PCI core to produce a bunch of debug
	  messages to the system log.  Select this if you are having a
	  problem with PCI support and want to see more of what is going on.

	  When in doubt, say N.

@ProMix0
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ProMix0 commented Apr 13, 2026

Have you tried loading the firmware from this directory?

No luck, same errors. I believe these firmware files use some another protocol for "handshake" between driver and FW. If it is slightly different, it might be easily fixed. If not... it will be harder

@jameywine
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No luck, same errors.

What about the multiFW.bin one?

I have checked the https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/rtw89 binary files and the multiFW.bin has the same sort of hex structure to them.

@ProMix0
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ProMix0 commented Apr 13, 2026

What about the multiFW.bin one?

Forgot this one. But it doesn't work as well

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3 participants