Skip to content
View joshual-xlnx's full-sized avatar

Block or report joshual-xlnx

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. verilog-eval verilog-eval Public

    Forked from NVlabs/verilog-eval

    Verilog evaluation benchmark for large language model

    Python 2 1

  2. xup_fpga_vivado xup_fpga_vivado Public

    Hands-on experience using Vivado with Xilinx FPGA hardware

    Verilog 1

  3. xup_high_level_synthesis_design_flow xup_high_level_synthesis_design_flow Public

    Forked from Xilinx/xup_high_level_synthesis_design_flow

    AMD Xilinx University Program HLS tutorial

    C 1

  4. xup_embedded_system_design_flow xup_embedded_system_design_flow Public

    Forked from Xilinx/xup_embedded_system_design_flow

    AMD Xilinx University Program Embedded tutorial

    Verilog

  5. 2023 2023 Public

    Forked from CCF-TCArch-CCC/2023

    HTML

  6. fm-demod-rtlsdr-pynqz2 fm-demod-rtlsdr-pynqz2 Public

    Forked from hfwang132/fm-demod-rtlsdr-pynqz2

    Hardware FM demodulation on PYNQ-Z2 with RTL-SDR.

    Jupyter Notebook