Studying new concept
CECS @ USC
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University of Southern California
- Los Angeles
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11:21
(UTC -07:00) - junsooki.com
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ee354-final-project-2048
ee354-final-project-2048 PublicA hardware implementation of the classic 2048 puzzle game in Verilog, featuring VGA display output and accelerometer-based tilt controls.
Verilog
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jaynathan2021/MurmurHash3-Accelerator
jaynathan2021/MurmurHash3-Accelerator PublicSystemVerilog implementation of a scalable multi-lane MurmurHash3 hardware accelerator evaluating throughput, energy efficiency, and bandwidth bottlenecks on FPGA.
VHDL 1
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