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After synthesis, the check a flow wants is the RTL against the netlist made from it. -sv elaborates both sides with slang, which knows no liberty cells, and -verilog reads no RTL expressions, so that takes a synthesis step on the gold side today. SvRtlAgainstALibertyGateNetlist asks for it in one run. It fails today; this is the request. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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A request with a failing test, not a fix.
After synthesis, the check a flow wants is the SystemVerilog RTL against the gate netlist made from it, in one run. Today:
-svelaborates both sides with slang, which knows no liberty cells, so the gate netlist fails to elaborate.-verilogreads gate netlists, but not RTL expressions.So the gold side needs a synthesis step first. bazel-orfs runs yosys with flops renamed after the RTL registers, so that LEC can pair them by name.
KeplerCliSubprocessTests.SvRtlAgainstALibertyGateNetlistinMiterTestschecksassign y = a & bagainstAND2 u (...), with a tiny inline liberty, using-sv -v sec --design1 rtl.sv --design2 gates.v --liberty tiny.lib. It fails today: slang reports one error and the netlist does not load. It runs in milliseconds.A possible shape:
--libertycells are made known to the-svfrontend as black-box modules with their liberty function, so a design mixing RTL and cells elaborates.🤖 Generated with Claude Code