[xtofalex]

Standard gate symbols, and a rework of how the schematic is laid out and wired.

Gate type and clock pins from naja's modeling

• primitive_type now also comes with resolve_instance / instance_resolved, so an instance shown on its own (focus_instance, "Show Instance") gets its gate symbol, not a box.
• Expanded terms carry "clock": true on a sequential cell's clock pin, so the DFF clock notch appears after "show all pins" too.
• Both come from SNLDesignModeling, never from cell or pin names. LocalSNLProvider.cpp and protocol.py are kept in step, with tests.
• scripts/gate_shapes_example.v: a small gate-level design with one instance of every recognized primitive, to check the symbols.

Schematic layout

The layout follows the usual schematic-generation pipeline. It lives in SchematicLayout, which is pure geometry with unit tests.

• Symbols (symbolGeometry): every pin sits on a 20-unit grid.
  • A gate is sized by its input count, with the inputs centered on the output. Its body (and negation bubble) fills its box exactly, so pin ticks always touch the body.
  • OR/XOR gates get a concave back.
  • A box is sized to fit its pin names, which are drawn inside it. Gate pins are unlabeled, except merged buses.
  • Instance names are drawn above the symbol.
• Placement (layeredPlacement, replacing IncrementalLayout):
  • cycles (flop feedback) are broken, and each instance gets a longest-path level; a source is pulled next to what it feeds;
  • each column is ordered by barycenter sweeps to cut crossings;
  • heights are chosen so connected pins line up, which gives straight wires.
• Routing (routeNets): one orthogonal tree per driving pin.
  • Vertical runs go in the box-free channels between columns, one track per net, so two nets never share a vertical line.
  • Tracks are ordered so two nets' horizontals at the same height never overlap either.
  • A long horizontal run detours around boxes, labels and other nets' runs.
  • Junction dots mark real branch points only.
• Ports sit on the sheet's left and right edges, level with the pin they connect to.
• Hierarchy frames keep each leaf's level, and where they can, the height that aligned its pins.

Behavior change

The layout is now recomputed from scratch every frame instead of built up net by net. It is deterministic, and ordering ties follow the order nets first appeared in, so nothing moves unless the nets change. But adding a net can shift boxes that are already drawn. A pin click still keeps the clicked box in place on screen.

Wiring inside an instance expanded in place (the +/- button) keeps its old simple drawing.

Tests

• SchematicLayoutTest: symbols, placement (straight chains, fan-in order, feedback, no overlaps on a random graph, determinism), port stacking, and routing (straight wires, junctions, separate tracks, same-height horizontals, detours, spine separation).
• The existing headless click tests (EquipotentialViewTest) pass unchanged.
• Placement plus routing takes about 3 ms per frame for a random 150-gate netlist.

🤖 Generated with Claude Code