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Prepare naja-scope 0.1.19 with najaeda 0.7.29 - #27
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Upgrade to najaeda 0.7.29 and adopt its new raw-API features: - Follow the camelCase-only raw binding: LogicCone getNodeCount/getNodes/ getLeaves and naja.intentAvailable/intentTypeOf/intentParametersOf/ intentPackageMember (snake_case aliases were removed upstream). - Source references: read the language-neutral getSourceDeclaration / getSourceOrigins, falling back to getSourceLoc. Gate-level Verilog netlists now answer get_source, and extra origins are listed as `origins`. - load_verilog(yosys_source_attributes=True) decodes Yosys src attributes into RTL origins; get_source(path, origin=N) reads them. - load_vhdl accepts a list of files loaded as one batch in any order. - load_systemverilog(blackbox_multi_writer_memories=True) blackboxes modules with unsupported multi-writer memories instead of failing. - Revalidate the CORE-V-MCU demo baseline (631,603 leaves) and record the CVA6 v5.3.0 / master recheck in CLAUDE.md.
naja-schematic 0.2.0 requires najaeda>=0.7.29, drops the deprecated is_clock() call, and adds Show Sources; pass the session's source directories as its source_roots.
najaeda 0.7.29's memory inference no longer lets the cone run through the AXI adapter's registered (non-fall-through) I/D-cache data FIFOs. The fan-in of cva6.noc_req_o now stops at 15 registers inside cache_subsystem.i_adapter (16,145 nodes); 0.7.27 over-approximated it at ~2.47M nodes reaching back into the caches. Assert that the frontier lives in the adapter instead of requiring a >100k-node cone.
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Upgrade to najaeda 0.7.29 and adopt its new raw-API features:
getLeaves and naja.intentAvailable/intentTypeOf/intentParametersOf/
intentPackageMember (snake_case aliases were removed upstream).
getSourceOrigins, falling back to getSourceLoc. Gate-level Verilog netlists
now answer get_source, and extra origins are listed as
origins.into RTL origins; get_source(path, origin=N) reads them.
with unsupported multi-writer memories instead of failing.
CVA6 v5.3.0 / master recheck in CLAUDE.md.
Tests: 120 passed (incl. the 3 CVA6 regressions on a v5.3.0 snapshot rebuilt under 0.7.29); CORE-V-MCU demo passes.
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