loader(safetensors): port MLA / Mixtral / Qwen-MoE loaders onto ISafetensorsTensorSource - #314

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jamesburton:issue/313-loader-interface-migration

Commits on Jun 6, 2026

vulkan: scaffold cross-vendor GPU compute backend (#155)

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loader(safetensors): binary parser foundation — File, DType, Descriptor (#154)

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vulkan: baseline F32 + Q8_0 compute kernels (#167)

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loader(safetensors): HfConfigExtractor + TransformerWeightsSafetensors for dense LLMs (#166)

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lora(core): LoRA Phase 4a foundation — core types + PEFT loader + CPU forward path (#164)

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core(moe): Mixtral-family MoE foundation — top-k routing + per-expert SwiGLU (#175)

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vulkan: add matmul_q8_0_gemm kernel (#173)
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vulkan: add bias_add_f32 kernel (#173)
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vulkan: fix matmul_q8_0 GEMV stride bug at K=32 with M>1 (#173)
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core(mla): MLA attention foundation — CPU PoC kernel + DeepSeek-V2/V3 config detection (#176)

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core(mla): wire DeepSeek-V2/V3 forward path end-to-end (#176)

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core(mla): apply YaRN softmax mscale² correction (P2.2) (#178)

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core(mla): Phase A expanded KV-cache (P2.3) (#178)

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core(mla): Phase B latent KV-cache + absorbed attention (P2.3) (#178)

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kernels(cpu): vectorise MLA attention inner loops via TensorPrimitives (#178)

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core(mla): Phase C hybrid cache — prefill expand + decode absorbed (P2.3) (#178)

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core(moe): Qwen-MoE — shared-expert support for Qwen1.5 / 2 / 3-MoE (#180)

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Merge remote-tracking branch 'origin/issue/166-safetensors-hf-config-extractor-dense-loader' into issue/181-lora-parity-tinyllama-tests
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lora(tests): forward parity + multi-adapter switch tests (Phase 4a) (#181)

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lora(tests): TinyLlama real-adapter integration test (Phase 4a) (#181)

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75a53e3

Commits on Jun 7, 2026

lora(server): API integration — request field + admin endpoints (#189)

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lora(server): multi-adapter batcher + endpoint/batcher unit tests (#189)

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core(moe): DeepSeek-V2/V3 multi-shared-expert support (#194)

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vulkan: scaffold transformer model, weights, KV cache, and forward state (#205)
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vulkan: reset descriptor pool after each Launch (#205)

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vulkan(perf): device-local weights + KV cache via staging (#206)

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vulkan(perf): fence-pipelined forward, one submit per forward (#206)

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vulkan(perf): descriptor-set cache per kernel (#206)

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vulkan: device-local activation scratch buffers (#206)

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Merge #164 (LoRA-1 core types) into base for Vulkan LoRA Phase 4b
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Merge #166 (safetensors HF dense loader) into base for Vulkan LoRA parity tests
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vulkan(lora): VulkanLoraAdapter device upload + handle cache — Phase 4b (#216)

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vulkan(lora): LoRA delta dispatch in Forward + per-projection wire-up — Phase 4b (#216)

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vulkan(lora): real TinyLlama LoRA parity vs CPU — Phase 4b (#216)

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engine: IModel.ForwardBatch API + per-sequence-loop default impl (#222)
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docs(scheduling, server): continuous-batch scheduler details (#222)
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Merge remote-tracking branch 'origin/issue/216-vulkan-lora-adapter' into issue/229-vulkan-lora-fused-delta
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vulkan(lora): fused delta GEMV shader (#229)

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vulkan(lora): kernel wrapper + tests (#229)

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vulkan(lora): dispatch refactor — fused delta path (#229)

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Merge origin/issue/178-mla-kv-cache-phases-mscale-simd into base for LoRA-5
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Merge origin/issue/194-moe-deepseek-multi-shared-expert into base for LoRA-5
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LoRA: F16/BF16 native adapter weights + MLA/MoE acceptance + perf bench (Phase 4d) (#238)

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LoRA: wire MLA and MoE deltas (#238)
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Merge remote-tracking branch 'origin/issue/229-vulkan-lora-fused-delta' into issue/PLACEHOLDER-lora-phase-4d-q8-outerprod
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LoRA bench: synthetic adapter fixture (#243)

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LoRA bench: macro-benchmark BDN class (#243)

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LoRA Phase 4d.4: spike decision — Q8_0 LoRA delta path (B-only) (#243)

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LoRA Phase 4d.4: Q8_0 LoRA-B kernel + adapter-load quantiser + parity tests (#243)

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LoRA Phase 4d.4: Q8_0 macro-bench wiring + asymmetric A/B dtype plumbing (#243)

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LoRA Phase 4d.4: Q8_0 path — rescue with dequant-once + macro-bench results (#243)

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LoRA Vulkan: Q8_0 upload path + dequant-on-load (Phase 4d.5 / Gap 1) (#243)
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LoRA CPU: pre-quantise-x once per layer (Phase 4d.5 / Gap 2) (#243)
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LoRA CPU: gate Q8_0 pre-quant-x fast path on env var (Phase 4d.5 follow-up) (#243)
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LoRA: outer-product stage-2 fast path + lazy transposed-A cache (Phase 4d.6) (#243)
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5110e67

Commits on Jun 8, 2026

Merge #243 (LoRA Phase 4d.6) into Phase 5a base
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TransformerModel: ForwardBatch CPU lm_head fusion (Phase 5a) (#276)

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TransformerModel: ForwardBatch CPU intra-block matmul fusion (Phase 5b) (#277)

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loader(safetensors): port MLA / Mixtral / Qwen-MoE loaders onto ISafetensorsTensorSource (#313)

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