CSE3016: 서강대학교 컴퓨터공학실험II 프로젝트 저장소

• Verilog codes for FPGA, using Vivado

week1

• Vivado 설치

week2

• Verilog 자료형 및 문법
  • Inverter, Buffer 구현

week3

• AND, OR 논리 게이트
  • 3,4 input AND/OR 게이트 구현

week4

• NAND, NOR, XOR 논리 게이트
  • 4 input NAND/NOR/XOR/AOI 게이트 구현

week5

• Boolean function and Demorgan's law
  • Boolean function, 1bit 비교기 구현

week6

• Adder and Subtracter
  • Full/Half Adder and Subtracter, 8421(BCD)-2421 code converter 구현

week7

• Parity Bit generator, checker
  • Parity bit generator/checker, 2bit binary comparator 구현

week8

• 7 segment Display
  • 7 segment Display 구현

week9

• Encoder, Decoder, Multiplexer, Demultiplexer
  • (4to2)Encoder, (2to4)Decoder, (4to1)Multiplexer, (1to4)Demultiplexer, (BCD to Decimal)Decoder 구현

week10

• 4bit Adder/Subtracter, BCD Adder(보상회로)
  • 4 bit Binary Parallel Adder/Subtracter, BCD Adder 구현

week11

• Latch and Flip-Flop
  • D/RS Flip-Flop 구현

week12

• Finite state machine and Counter
  • Binary Counter, 4bit Decade Counter, 2421 Decade Counter 구현

week13

• Register and Counter
  • 4bit Shift Register, 4bit Ring Counter, Up/Down Counter 구현

Week14 : Sequence Detector : Mealy and Moore

1101 Sequence Detector Mealy Machine 구현