[ROCm][DSv4][WIP] Sparse-MLA bring-up on MI300X (FP8 encoder/decoder symmetry + cudagraph fixes)#1
[ROCm][DSv4][WIP] Sparse-MLA bring-up on MI300X (FP8 encoder/decoder symmetry + cudagraph fixes)#1maeehart wants to merge 283 commits into
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… operand layout with WGMMA (vllm-project#42076) Signed-off-by: kermit <ckeming@outlook.com>
…ng CUDA graph capture failure (vllm-project#42070) Signed-off-by: Thomas Parnell <tpa@zurich.ibm.com> Co-authored-by: Jiangyun Zhu <riverclouds.zhu@qq.com>
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…ivations) support (vllm-project#41769) Signed-off-by: Juhi Mittal <juhim@nvidia.com>
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…atures without `KVCacheConfig` (vllm-project#39832) The v0.12.0 release contained initial support for HMA in KV Connectors. As part of these changes, a KVCacheConfig argument was added to KV connector constructors. Backwards compatibility support for out-of-tree connectors was included in this change, with a very prominent warning. See vllm-project#25712 and vllm-project#27887. Since the warning has been around for over 5 months, we can safely remove the support of it. Signed-off-by: yewentao256 <zhyanwentao@126.com>
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…to free stranded KV blocks (vllm-project#41269)
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…le attribute paths (MoE gate) (vllm-project#42757) Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
Signed-off-by: ganyi <ygan@amd.com> (cherry picked from commit 1be2b74)
Signed-off-by: ganyi <ygan@amd.com> (cherry picked from commit 80fed5b)
cmake/utils.cmake unconditionally renames every .cu in a HIP target's
source list to .hip and lists those names as BYPRODUCTS of the
hipify${NAME} custom target. torch.utils.hipify.hipify_python only emits
a hipified_path when it actually replaces something; for files that are
already pure HIP (e.g. csrc/rocm/attention.cu only references __HIP__
APIs and uses HIP types directly), the result keeps the original .cu
name and no .hip file is written.
That mismatch is invisible during a wheel build where the file is
covered by something earlier in the dependency graph, but for an
editable install (pip install -e .) the compile step runs against the
BYPRODUCT path and fails with:
clang++: error: no such file or directory:
.../build-temp/csrc/rocm/attention.hip
Mirror the file to the expected .hip path when hipify reports "no
changes" so the BYPRODUCT exists. This is a no-op for files that hipify
already rewrote; for pure HIP sources it just costs one extra copy.
Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
DeepseekV4DecoderLayer.__init__ no longer creates ``self.ffn_norm``; the FFN pre-norm is folded into ``self.ffn.norm_gate`` (NormGateLinear) and ``self.ffn(x, input_ids)`` consumes the pre-norm activation directly. ``_forward_cuda`` was updated accordingly when the fold landed, but ``_forward_rocm`` still calls ``self.ffn_norm(x)``, which trips the moment ROCm tries to dummy_run the model: AttributeError: 'DeepseekV4DecoderLayer' object has no attribute 'ffn_norm' Drop the stale call so the ROCm path matches the CUDA path's expected flow through the FFN. Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
The DSv4 sparse MLA Triton kernels added in vllm-project#41812 (and the matching turboquant store/decode kernels) bitcast uint8 to ``tl.float8e4b15`` when ``IS_FNUZ`` is true. ``float8e4b15`` is not a real Triton type; on AMD gfx942 (MI300X) Triton only supports the FP8 dtypes listed in the error from triton/compiler: ('fp8e4b8', 'fp8e4nv', 'fp8e5', 'fp8e5b16') The correct FNUZ E4M3 type is ``tl.float8e4b8`` (bias 8, matches the PyTorch ``torch.float8_e4m3fnuz`` used elsewhere on the MI300 path). The non-FNUZ branch already correctly uses ``tl.float8e4nv``. Without this fix, the very first profile run on MI300X with sparse MLA fails inside the dequant/gather kernel: type fp8e4b15 not supported in this architecture. This swaps all FNUZ branches to ``tl.float8e4b8``. Verified that ``IS_FNUZ`` is gated on ``current_platform.fp8_dtype() == torch.float8_e4m3fnuz`` so it never fires on OCP hardware. Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
The DSv4 sparse MLA path has two K caches with different writers:
1. compressed_k_cache: written by Triton
_fused_kv_compress_norm_rope_insert_sparse_attn, which uses
tl.float8e4nv with FP8_MAX=448.0 hardcoded -- OCP bytes on every
platform.
2. swa_k_cache: written by the C++ kernel
fused_deepseek_v4_qnorm_rope_kv_rope_quant_insert, which after
6d6c6e4 ("accuracy right") switches to __hip_fp8_e4m3_fnuz and
kFp8Max=240.0 on gfx942, OCP otherwise.
Commit 5f22bea ("mi300 support") added use_fnuz=is_fp8_fnuz() to
both dequant calls, but only the SWA-side encoder was actually changed
to FNUZ. The compressed-side call therefore read OCP-encoded bytes back
as FNUZ on MI300X, which scrambled every context K vector. End-to-end
the model still produced grammatical English -- it just emitted prior-
training fragments because the attention had lost all input information
("The capital of France is" -> Creative Commons boilerplate).
Match the compressed dequant to its encoder: keep use_fnuz=False for
the compressed call (Triton OCP on every platform) and leave the SWA
call on use_fnuz=is_fp8_fnuz() so it tracks the C++ encoder's gfx950
gate. A comment explains the asymmetry so the next reader doesn't try
to unify them again.
Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Plan A (decoder-side use_fnuz=False) only fixed short-prompt outputs
that never trigger the compressor. Once the compressor fires (longer
sequences, compress_ratio*overlap+ tokens) attention output reverted to
hallucinated training-data fragments and even diverged between identical
deterministic requests, which points to corrupted bytes in the
compressed K cache rather than a layout mismatch.
The cherry-picked C++ kernel patch ("accuracy right", 6d6c6e4)
already documented the underlying constraint: gfx942 MFMA only supports
FNUZ FP8, and Triton's `tl.float8e4nv` cast on that arch silently
lowers to FNUZ instructions. So the encoder was writing FNUZ bytes
all along, the SWA-side C++ encoder was changed to FNUZ explicitly,
but the Triton compressor encoder still used FP8_MAX=448.0 (OCP max)
in the scale arithmetic. That scaling mismatch is what corrupted the
compressed K values.
Make the encoder symmetric with the decoder on FNUZ-only hardware:
- Add a `USE_FNUZ` constexpr to the three
`_fused_kv_compress_norm_rope_insert_*_attn` kernels in
`fused_compress_quant_cache.py`. Sparse and indexer-attn paths use
it to switch the final cast between `tl.float8e4nv` (OCP) and
`tl.float8e4b8` (FNUZ); the MXFP4 path accepts the flag for signature
parity but doesn't need it (no FP8 cast).
- In `deepseek_compressor.py`, plumb `FP8_MAX=240.0` (FNUZ max) and
`USE_FNUZ=True` whenever `current_platform.is_fp8_fnuz()`. Keep the
old 448.0 / OCP path for everyone else.
- Revert the previous Plan-A workaround in
`deepseek_v4_attention.py` so both compressed-K and SWA dequant
paths once again use `use_fnuz=current_platform.is_fp8_fnuz()`.
Encoder and decoder are now in agreement on FNUZ-only hardware.
The other Triton FP8 writers in the DSv4 op set still use
`tl.float8e4nv` and 448 hardcoded. They feed kernels (AITER MQA logits,
DeepGEMM scaled MM) that read `torch.float8_e4m3fn` and decode via
`tl.float8e4nv` themselves, so encoder and decoder there are already
consistent (whichever underlying op Triton actually emits on gfx942,
it round-trips). If subsequent tests show those paths are also wrong,
the same `USE_FNUZ` plumbing can be extended in a follow-up.
Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
The DSv4 sparse indexer pipeline encodes Q via ``_fused_indexer_q_rope_quant_kernel`` and feeds the resulting ``torch.float8_e4m3fn`` tensor to the AITER ``fp8_mqa_logits`` kernel (which reads it as ``tl.float8e4nv``). On gfx942 the Triton cast that produces those bytes silently lowers to FNUZ instructions, but the encoder still scales with ``FP8_MAX=448.0`` and casts to ``tl.float8e4nv``, and the output tensor stayed ``torch.float8_e4m3fn``. Result on MI300X: the indexer Q values are FNUZ-encoded but the downstream reader interprets them as OCP, so the per-token topk logits are scrambled and attention selects nearly-random positions. Plan-B's compressed-K encoder fix improved end-to-end output (model now stays topical), but factual answers still degrade because the topk selection is still wrong. Plumb ``FP8_MAX`` and ``USE_FNUZ`` constexprs through the kernel and keep the output tensor dtype, the cast target, and the saturation max in agreement: - Cast to ``tl.float8e4b8`` and saturate at 240.0 when FNUZ. - Stay on ``tl.float8e4nv`` / 448.0 on OCP hardware. - Allocate ``index_q_fp8`` as ``torch.float8_e4m3fnuz`` on FNUZ so the consumer (Triton dot with ``input_precision="ieee"``) decodes with the same bias as the encoder. This change only touches the FP8 indexer path (``_fused_indexer_q_rope_quant_kernel``); the MXFP4 path is unchanged because it produces packed nibbles plus per-block ue8m0 scales rather than an FP8 tensor. Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
``_fused_inv_rope_fp8_quant_per_head`` produces the FP8 activation that feeds the wo_b einsum at the end of every sparse-MLA attention block. Like the other DSv4 Triton encoders, it hardcoded ``tl.float8e4nv`` and ``torch.float8_e4m3fn``, and computed ``fp8_max`` from the OCP finfo. On gfx942 (MI300X) where Triton silently lowers those casts to FNUZ, this means every attention output was encoded under FNUZ semantics but read back by ``fp8_einsum`` (and its DeepGEMM/AITER paths) as OCP, adding a per-layer numeric mismatch that accumulated across the model. Thread the FNUZ flag the same way as the compressor and indexer-Q kernels: - Add ``USE_FNUZ: tl.constexpr`` to ``_fused_inv_rope_fp8_quant_per_head`` and select between ``tl.float8e4b8`` / ``tl.float8e4nv`` for the final cast. - In the impl + fake registered as the custom op, allocate ``fp8_buf`` with ``current_platform.fp8_dtype()`` (FNUZ on MI300X) and pass ``USE_FNUZ=current_platform.is_fp8_fnuz()`` when launching. - Compute ``fp8_max`` from the platform-aware ``fp8_dtype()`` so the scale-arithmetic upper bound (240.0 vs 448.0) matches the cast and the downstream einsum's expectations. Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
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``_forward_prefill_attn`` allocates the prefill KV buffer via ``current_workspace_manager().get_simultaneous`` which returns a ``torch.empty`` view -- uninitialized memory shared across requests and across earlier layers in the same forward pass. For each chunk row only the compressed-K prefix (rows [0, seq_len / compress_ratio)) and the SWA window (rows [N, N + gather_lens)) get written by ``dequantize_and_gather_k_cache``. The rest of the M dimension stays at whatever bytes the workspace held last. ``flash_mla_sparse_fwd`` then reads ``kv.view(-1, 1, head_dim)`` using ``combined_indices`` that can address those holes when a query token's effective context is shorter than M, so the attention output becomes data-dependent on prior workspace residents. Concrete symptom: on MI300X with FNUZ FP8 + cudagraphs, the same temperature=0 deterministic prompt produces 10 distinct first tokens across 10 back-to-back ``/v1/completions`` calls. Disabling AITER MoE and MLA did not help; the variance comes from this DSv4-specific workspace read. Zero ``kv`` once after ``get_simultaneous`` so any unread slot deterministically contributes zero. The cost is one bf16 fill of ``PREFILL_CHUNK_SIZE * M * head_dim`` bytes per attention layer call, which is dwarfed by the FP8 dequant + sparse FlashMLA themselves. Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
``DeepseekV4ROCMAiterMLASparseImpl._forward_prefill_attn_impl`` in ``vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse_dsv4.py`` is the actual ROCm path reached from ``DeepseekV4MLAAttention.forward`` at ``deepseek_v4_attention.py:762`` (``current_platform.is_rocm()``). ``DeepseekV4MLAAttention._forward_prefill`` in the same file is dead code on ROCm, so the previous ``kv.zero_()`` patch (commit 36a7037) fixed only the generic path. This ROCm-only forward also gets ``kv`` via ``current_workspace_manager().get_simultaneous(...)`` -- uninitialized shared memory reused across requests and layers -- writes only the compressed-K prefix and the SWA window for each chunk row, then reads the entire ``kv.view(-1, 1, head_dim)`` through ragged indices that can land on the holes for very short sequences. The result is exactly the symptom we observe on MI300X DSv4-Flash: 10 identical temperature=0 ``/v1/completions`` calls produce 10 distinct first tokens. Apply the same zero-init here. Cost is one bf16 fill of the workspace tile, dwarfed by the FP8 dequant + sparse attention. Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
The attention output buffer ``o_padded`` is allocated as ``torch.empty((num_tokens, padded_heads, head_dim))`` with ``padded_heads`` being the FlashMLA-required head count (64 or 128). On a TP=4 8-node deployment ``n_local_heads = 32 < padded_heads = 128``, so the attention kernel only writes the first 32 rows of dim 1 and leaves the trailing 96 rows holding whatever bytes the caching allocator returned. ``o = o_padded[:, : n_local_heads, :]`` slices those rows off, but pre-FP8-quant + warp-collective reductions in the inverse-RoPE + einsum path observed non-determinism that tracks allocator state across requests. Switch to ``torch.zeros`` to make the trailing rows a fixed sentinel. The observable downstream computation only touches the sliced view; this change just removes one source of cross-request entropy while we hunt down the residual non-determinism on MI300X DSv4-Flash. Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
Probed whether zero-initializing the attention output buffer would remove the across-request non-determinism we still see on MI300X DSv4 after the workspace kv zero-init in commits 36a7037 / 0cca642. Running the 10-prompt /v1/completions diagnostic with this change showed the same pattern (10 distinct first tokens for 10 identical temperature=0 calls), so o_padded is not the source. Revert to torch.empty to avoid an unnecessary fill on the hot path. Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com> Co-authored-by: Cursor <cursoragent@cursor.com>
Summary
Bring up DeepSeek-V4 sparse-MLA on MI300X (gfx942) using the
ROCm/AITER vLLM stack. End-to-end the model now runs with TP=4,
--kv-cache-dtype fp8,VLLM_ROCM_USE_AITER=1, and cudagraphFULL_AND_PIECEWISEenabled, and produces coherent topical output(
"capital of France" -> Paris,"largest planet" -> Jupiter,"27 times 43 = 1161"correct on some samples). Accuracy is stilldegraded vs CUDA baseline (GSM8K@200 ~1-2%), which is being tracked
as follow-up FP8 work outside the DSv4-specific Triton kernels (FMOE,
linear). Throughput at ISL=1000/OSL=100, max-concurrency=16 is
~301 tok/s output / ~3300 tok/s total on a single MI300X node.
What's in this branch
Two cherry-picks from @ganyi1996pku in
vllm-project#41451
provide the C++ kernel + initial MI300X plumbing, and a set of
follow-on commits make the DSv4-specific Triton kernels and Python
glue symmetric on FNUZ-only hardware.
Commits vllm-project#6 and vllm-project#7 should be squashed before any upstream submission;
the standalone Plan-A change reverts cleanly inside Plan-B and is kept
here only so the bring-up narrative is reproducible.
Root cause story (what the FP8 commits fix)
DSv4 sparse-MLA touches four distinct FP8 encoders, all writing into
buffers that downstream Triton/AITER readers interpret as
tl.float8e4nv(OCP). On gfx942 MI300X the MFMA instructions onlysupport FNUZ, so Triton silently lowers
.to(tl.float8e4nv)caststo FNUZ. That means the bytes in those buffers were FNUZ-encoded but
the readers interpreted them as OCP. The four mismatched paths and
their fixes:
Compressed-K cache (this PR commits Support beam search & parallel generation vllm-project/vllm#7 + retired Automatically configure KV cache size vllm-project/vllm#6) -
_fused_kv_compress_norm_rope_insert_sparse_attn/_fused_kv_compress_norm_rope_insert_indexer_attn(Triton) wrotebytes with
FP8_MAX=448.0andtl.float8e4nv. Decoder(
dequantize_and_gather_k_cache) reads them back. On MI300Xboth now use
USE_FNUZ=TruewithFP8_MAX=240.0and the casttarget
tl.float8e4b8; the decoder keepsuse_fnuz=current_platform.is_fp8_fnuz().SWA-K cache (already correct after cherry-pick Support tensor parallel vllm-project/vllm#2) - C++ kernel
fused_deepseek_v4_qnorm_rope_kv_rope_quant_insertnow writesFNUZ-encoded bytes on gfx942 and OCP elsewhere; decoder uses
use_fnuz=current_platform.is_fp8_fnuz().Sparse indexer Q (this PR commit Add miscellaneous updates vllm-project/vllm#8) -
_fused_indexer_q_rope_quant_kernelwas producing bytes consumedby AITER's
fp8_mqa_logits. PlumbedFP8_MAXandUSE_FNUZconstexprs through the kernel; on FNUZ hardware it casts to
tl.float8e4b8withFP8_MAX=240.0and the tensor dtypebecomes
torch.float8_e4m3fnuzso the dot-product reader usesthe matching bias.
Sparse-attention output (this PR commit Implement LLaMA vllm-project/vllm#9) -
_fused_inv_rope_fp8_quant_per_headfeeds the wo_b einsum at theend of every block. Same shape of fix:
USE_FNUZconstexpr,current_platform.fp8_dtype()for the buffer,fp8_maxfromthe platform-aware finfo.
Verification
Container:
vllm-dsv4-mi300onchi-mi300x-004(single MI300Xnode, TP=4). Launch (in
/host_logs/run_smoke.sh):Environment:
VLLM_ROCM_USE_AITER=1,HIP_VISIBLE_DEVICES=0,1,2,3, AITERfp8_mqa_logitspatched toBLOCK_KV=64in the container's installedaiterpackage (gfx942has 64 KB LDS / CU; the upstream 128 wants 96 KB).
Smoke (
/host_logs/dsv4_smoke.sh, three back-to-back runs)Sample outputs (max_tokens=32, temperature=0):
The non-determinism between identical deterministic requests
(temperature=0) suggests residual workspace / state-cache uninitialised
memory; documented as follow-up.
lm_eval gsm8k
Both with --num_fewshot=5 against the running server:
Coherent end-to-end output but precision is still off; the next
FP8 paths to audit are AITER FMOE and the FP8 block-quant linear
weights (fp8.py / process_weights_after_loading).
vllm bench serve ISL=1000/OSL=100, max-concurrency=16
What's still broken (next steps)
audit on FNUZ hardware:
vllm/model_executor/layers/quantization/fp8.py-process_weights_after_loadingalready handles UE8M0 and FNUZfor scales but the activation quant in
Fp8LinearOpshould be double-checked end-to-end.fp8_einsumconsumer of the inv-rope output (DeepGEMM /AITER) - now reads FNUZ buffers, verify GEMM-side bias.
BLOCK_KV=64patch lives in the container's installedaiterpackage, not under git. Either upstream a small AITER PRgating BLOCK_KV on shared-memory budget, or expose a kwarg in
rocm_aiter_mla_sparse.pyso callers can pick the safe block.in
--enforce-eagermode. Suspect: a workspace tensor allocatedwith
torch.emptyand only partially overwritten when seq-lengthpadding kicks in. Worth bisecting once accuracy is restored.
above is fixed - infrastructure (build, container, run scripts)
is in place at
conversations/vllm-fp8-mla-dense-prefill-pr42509/.Attribution
The C++ kernel + initial wiring for DSv4 sparse-MLA on MI300X were
written by @ganyi1996pku in
vllm-project#41451;
cherry-picks #1 and vllm-project#2 in the table above are theirs. The Triton
encoder / decoder symmetry fixes and the build/cudagraph adjustments
are mine.
Test plan
/host_logs/dsv4_smoke.sh) - model produces coherenttopical output across multiple back-to-back runs.
lm_eval gsm8k --limit 200 --num_fewshot 5- completes; resultrecorded above (1% flexible-extract).
vllm bench serveISL=1000/OSL=100 max-concurrency=16 -completes; result recorded above.
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