[masarray]

Summary

Bring ARStack61850 Sampled Values onto real ESP32-P4 Ethernet hardware and advance the proven P0/P1 path into the P2 50 Hz realtime publisher foundation.

Hardware evidence proven

• ESP32-P4 rev 1.3 boots with the pre-v3 ESP-IDF revision profile.
• Onboard RMII PHY link comes up and raw Layer-2 frames reach the capture host.
• Independent packet capture decodes emitted 0x88BA frames as IEC 61850 Sampled Values.
• GPTimer-driven 50 Hz publisher sustains about 4000 frames/s with no device-side missed slots in the current bench test.
• Busy-spin scheduling was replaced by a 1 MHz GPTimer + FreeRTOS task notification so CPU1 no longer starves IDLE1 / Task WDT.
• A raw process-bus analyzer reconstructs balanced 50 Hz three-phase waveforms from the diagnostic stream and reports continuous sequence integrity.
• The current USB-Ethernet host capture path reports about 3999 fps but also large individual arrival-time excursions. Those host capture timestamps are therefore treated as capture-path evidence, not device-TX timing proof.

SCL-aligned canonical stream

The standards-facing stream is aligned to 01_SV_Stream_4I+4V_(9-2LE).scd stream #1:

• destination 01:0C:CD:04:00:01
• APPID 0x4000
• VLAN PCP 4 / VID 0
• svID=MU01_SV1
• confRev=1
• one ASDU
• 4000 samples/s, 80 samples/cycle at 50 Hz
• dataset layout Ia, Ib, Ic, In, Ua, Ub, Uc, Un, each INT32 instMag.i + UINT32 Quality
• dataset reference omitted in the ASDU because the supplied SCL has dataSet=false
• smpRate/smpMod omitted from the canonical ASDU because the supplied SCL has sampleRate=false
• smpSynch=0 remains truthful until PTP/1PPS lock is implemented and measured

Lab-only diagnostic stream

The tested host capture path reliably exposes broadcast traffic but does not reliably expose the canonical multicast/VLAN stream. A separate diagnostic stream is therefore available:

• untagged broadcast
• APPID 0x4F01
• svID=AR_DIAG_SV1
• explicit smpRate=4000, smpMod=SmpPerSec
• independent normal 16-bit smpCnt

The separate identity prevents raw analyzers from merging canonical and mirror traffic and avoids false sequence alarms caused by applying a 65536-counter assumption to a 4000-wrap canonical stream. The diagnostic stream is not an IEC 61850 process-bus compliance target.

P2 50 Hz realtime foundation

• 50 Hz / 80 samples per cycle / 4000 frames per second.
• GPTimer 1 MHz periodic alarm every 250 us.
• ISR only notifies a dedicated high-priority publisher task; publisher blocks between alarms.
• Prebuilt fixed-size packet templates; no BER encoding or heap allocation in the TX hot path.
• Fixed runtime patch fields for 2-byte smpCnt, 4-byte confRev, and 64-byte seqData.
• Balanced sine generator for Ia, Ib, Ic, In, Ua, Ub, Uc, Un.
• Current payload scaling 1 mA/count and voltage payload scaling 10 mV/count.
• Default source: 1 A RMS current and about 57.74 V RMS phase-to-neutral (100 V line-to-line).
• Once-per-second scheduler/TX telemetry for submissions, TX failures, missed timer notifications, and wake lateness.

Standards-first next architecture

The next stage is intentionally not more hard-coded relay-specific patches. The embedded target documents a standards-first architecture that keeps wire facts, configured expectations, profile claims, and PTP/synchronization evidence distinct.

Planned direction in #24:

• compile an immutable/versioned SvPublisherProfile from SCL on the host;
• keep XML/SCL parsing out of the ESP realtime path;
• support explicit Generic IEC 61850-9-2, IEC 61869-9, and Legacy 9-2LE compatibility families without silently promoting heuristics to compliance claims;
• use ESP32-P4 EMAC IEEE1588v2 hardware time for TX timing evidence;
• build IEC/IEEE 61850-9-3 PTP monitoring/discipline and derive smpSynch from measured lock state.

See NORTH_STAR.md, PROJECT_HANDOFF.md, and embedded/esp32p4_smv_injector/ARCHITECTURE.md.

Public-repository naming policy

Project-owned public documentation is vendor-neutral. Commercial competitor/product names, comparison tables, logos, screenshots, and marketing references are intentionally excluded. Standards and technical platform/dependency identifiers required to build or reproduce the project are allowed.

Important boundary

This is not yet a final strict 9-2LE/IEC 61869-9 compliance claim. Remaining acceptance includes sustained 4000 fps hardware capture, hardware TX timestamp evidence, canonical multicast/VLAN capture on a trusted path, 60 Hz / 4800 fps, PTP/1PPS synchronization, SCL-driven profile deployment, and independent relay/tool interoperability.

Use only on an isolated lab process-bus bench or direct capture/TAP connection; do not connect this development image to an operational substation process bus.

Tracks deterministic timing evidence in #21 and standards-first SCL/profile/PTP work in #24.

[chatgpt-codex-connector]

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[chatgpt-codex-connector]

Filter on the VLAN-encapsulated EtherType

Because make_smoke_frame() adds an 802.1Q tag, a packet-capture dissector exposes the outer Ethernet type as 0x8100 and the encapsulated SV type as vlan.etype; therefore filtering only on the outer field can hide the emitted SV frames. Use vlan.etype == 0x88ba, or include both fields if untagged frames must also be shown.

[masarray]

CI update: the ESP32-P4 target now builds successfully on the pinned ESP-IDF version after isolating the Ethernet default-config macros in a C board adapter. Portable C++ CI is also green on the supported compiler matrix, and sanitizer/fuzz evidence jobs pass.

Software P0/P1 is therefore build-clean. I am deliberately leaving this PR open until the physical board acceptance is captured: flash the ESP32-P4 Ethernet target on an isolated bench/direct capture NIC, verify link-up and 0x88BA Sampled Values in an independent packet capture, then save the PCAP. That capture will close the P0/P1 hardware gate before the 4000/4800 fps P2 timing engine is allowed to claim real-time behavior.

[masarray]

Hardware log review found a real P2 scheduler defect: the 250 us busy-wait publisher monopolized CPU1, starving IDLE1 and tripping the Task Watchdog every ~5 s. The board was otherwise reaching ~4000 fps with zero TX API failures, but each watchdog episode introduced burst missed slots / rate dips, so that implementation is not acceptable timing evidence.

Fixed in commits db44bf9 + 8ecbed0: P2 cadence now comes from a 1 MHz ESP-IDF GPTimer periodic 250 us alarm. The ISR only gives a FreeRTOS task notification; the CPU1 publisher blocks between alarms, so IDLE1 can run/feed TWDT. Accumulated notifications are counted as missed sample slots, preserving truthful counter/timing telemetry. The hot path remains prebuilt-frame patch + esp_eth_transmit, with no BER allocation.

All three CI gates are green at head 8ecbed0, including the ESP32-P4 firmware build. Next hardware acceptance: flash this head, confirm no Task WDT messages over >=60 s, ~4000 fps, zero TX failures, then inspect reconstructed waveform and capture timing with an independent analyzer/capture path.