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M3C.4: compensate GPTimer START setup latency against PTP second - #229

Merged
masarray merged 5 commits into
feature/esp32p4-smv-ptp-epoch-binding-m3c-20261015from
fix/ptp-m3c-start-latency-epoch-20261017
Oct 17, 2026
Merged

masarray merged 5 commits into
feature/esp32p4-smv-ptp-epoch-binding-m3c-20261015from
fix/ptp-m3c-start-latency-epoch-20261017

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@masarray

@masarray masarray commented Oct 17, 2026 •

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Physical capture motivation

120-second user-supplied Windows ASIX/Npcap AUTO capture: 480,279 canonical SV + 480,278 diagnostic mirror, 0 discontinuities per stream, smpSynch=0 on every SV, 120 each PTP Announce/Sync/Follow_Up. Current public main does not implement continuous PTP–SV phase authority; it cannot claim LOCK. This PR is stacked on experimental M3 Draft #166, not public main.

Root cause and fix

Experimental plan_ptp_epoch_arm() read EMAC PTP before GPTimer setup but used the original delay unchanged when starting GPTimer later. GPTimer setup latency thereby shifts sample-zero away from the intended integer PTP second. Retain the after-read monotonic timestamp; rebase alarm at the latest pre-arm moment; validate same PTP source-scoped clock lease at handoff. If too close to a boundary, defer one full PTP second; reject stale/nonmonotonic evidence and revert to ordinary free-running START.

Guardrails

  • No new ISR work, transport TX, runtime parser, app UI, or change to 4000fps/smpCnt scheme.
  • smpSynch=AUTO stays 0; SOURCE class 248 is not globally traceable.
  • Portable tests cover compensated startup, deferred epoch, stale/malformed input.
  • Physical GM/PPS phase evidence, actual MAC SV egress timestamp and IED acceptance missing. Software CI must not be interpreted as PTP-locked.

Gate

Run exact-head PTP Core gcc/clang/MSVC, ESP32-P4 firmware SOURCE/RECEIVER, and negative regression. Evaluate bench afterwards; do not auto-merge into main.

Bench checkpoint request

[run-phase-guard]

Produce separately packaged SOURCE/RECEIVER firmware for isolated ESP32-P4 P0 physical evaluation. The existing guarded CI job enables experimental phase steering and sparse MAC TX descriptor evidence, disables the broadcast mirror, and retains fail-closed AUTO=0. Never publish as production firmware.

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📝 Code Review ✅ Completed 2026-10-17T11:24:49.310777Z 66413ba Draft marked ready
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@masarray
masarray marked this pull request as draft October 17, 2026 11:17

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2026-10-17 user-provided AUTO bench-capture checkpoint (isolated ASIX/Npcap, raw file retained by operator, not attached publicly): classic PCAP SHA-256 a3c40847cdd244178b7f026ebd1f11e8e2078a56d7ca90f8bbe44236487af82b, 960,936 total frames. Canonical SV APPID 0x4000: 480,279 frames, smpCnt wrap 120, no counter gap/duplicate/out-of-order; untagged diagnostic mirror APPID 0x4F01: 480,278 frames separately continuous. Both have smpSynch=0 throughout. PTP domain 0: 120 Announce + 120 Sync + 120 matching Follow_Up, zero Pdelay observed; existing SOURCE has class248/unknown accuracy. ASIX capture reports 0 pcap drops.

Diagnostic host-relative circular phase between captured canonical smpCnt=0 arrivals and PTP Sync hardware-origin fractional time, after pairing Sync/Follow_Up, is approximately -488.7ms (nearest PTP second), with observed narrow scatter. Because the SV timestamp is Npcap software RX (not actual SV MAC TX) and PTP SOURCE is untraceable, this cannot certify absolute phase; the large systematic offset does reinforce that the current v0.1.1 main firmware (no continuous servo) is not phase-locked. The user's WPF passive snapshot claimed one out-of-seq event, not corroborated by canonical PCAP/CSV counter continuity.

This PR addresses one concrete defect in the experimental first epoch arm: previously scheduled timer delay failed to subtract time spent configuring GPTimer. It does not guarantee a zero-offset physical phase, enable smpSynch promotion, or satisfy independent GM/PPS/IED acceptance. The bench-only guarded build is being prepared with phase servo ON and mirror OFF, separate from public firmware.

@masarray
masarray marked this pull request as ready for review October 17, 2026 11:22

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💡 Codex Review

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Reviewed commit: 66413ba420

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Comment on lines +618 to +622
const std::int64_t pre_arm_us = esp_timer_get_time();
const auto corrected_arm = epoch_arm.has_value() && pre_arm_us >= 0
? rebase_sv_ptp_second_arm(
epoch_arm->timer, epoch_arm->clock_read_after_us,
static_cast<std::uint64_t>(pre_arm_us))

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P1 Badge Move the rebase timestamp past the final lease check

When the final lease snapshot takes time or this task is preempted, remaining is computed from pre_arm_us before read_ptp_epoch_clock_lease(), while the GPTimer countdown starts only after that read and the subsequent alarm/enable calls. That unaccounted interval becomes a persistent sample-zero phase offset, and a delay exceeding the 20 ms lead can place smpCnt=0 after the intended PTP boundary while epoch_armed remains true. Capture/rebase the monotonic timestamp after the lease check and as close as possible to gptimer_start().

AGENTS.md reference: AGENTS.md:L94-L94

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@masarray
masarray merged commit b57392a into feature/esp32p4-smv-ptp-epoch-binding-m3c-20261015 Oct 17, 2026
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