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LLVM 19.1.0: Fixes #60

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2a53447
pattern-gen: ignore TargetOpcode::G_CONSTANT_FOLD_BARRIER
PhilippvK Apr 8, 2025
9f02fee
pattern-gen: do not print invalid patterns
PhilippvK Apr 8, 2025
331da4d
[pattern-gen] Parser: fix poison mask in gen_subscript
PhilippvK Oct 20, 2025
ecb8556
PatternGen: support X[0] in parser
PhilippvK Jan 22, 2026
d682824
[pattern-gen] Handle G_SELECT in traverseRegLoad
PhilippvK Oct 22, 2025
acfb306
PatternGen: expose --print-mir
PhilippvK Oct 29, 2025
915d0a7
[pattern-gen] Write optimized llvm-ir to irOut
PhilippvK Oct 22, 2025
2dbd2d3
llvm/lib/CodeGen/GlobalISel/PatternGen.cpp: add missing LLVM_DEBUG
PhilippvK Feb 17, 2026
f7e2a3f
llvm/tools/pattern-gen: parse attribute values (and support llvm_type)
PhilippvK Feb 2, 2026
d90c2ca
llvm/lib/CodeGen/GlobalISel/PatternGen.cpp: handle llvm_type
PhilippvK Feb 2, 2026
6210b25
llvm/tools/pattern-gen/CMakeLists.txt: add RISCVCodeGen & RISCVDesc deps
PhilippvK Mar 8, 2026
2f4cfe5
PatternGen: print mnemonic for instr
PhilippvK Jul 30, 2026
81a5f3e
[pattern-gen] Add hasSideEffects var
PhilippvK Aug 19, 2026
c4cdfd3
[pattern-gen] use CurInstr->llvm_instr for output
PhilippvK Aug 19, 2026
902072e
[pattern-gen] use instr.llvm_instr in InstrFormat
PhilippvK Aug 19, 2026
2f63e48
core_descs: update check lines to include mnemonic
PhilippvK Aug 19, 2026
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16 changes: 8 additions & 8 deletions core_descs/Example.core_desc
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,8 @@ InstructionSet XExample extends RISCVBase {

instructions {

// CHECK-RV32: Pattern for CV_SUBINCACC: (add (sub (add GPR:$rs1, (i32 1)), GPR:$rs2), GPR:$rd)
// CHECK-RV64: Pattern for CV_SUBINCACC: (add (sub (add GPR:$rs1, (i64 1)), GPR:$rs2), GPR:$rd)
// CHECK-RV32: Pattern for CV_SUBINCACC [cv.subincacc]: (add (sub (add GPR:$rs1, (i32 1)), GPR:$rs2), GPR:$rd)
// CHECK-RV64: Pattern for CV_SUBINCACC [cv.subincacc]: (add (sub (add GPR:$rs1, (i64 1)), GPR:$rs2), GPR:$rd)
CV_SUBINCACC {
encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
Expand All @@ -19,8 +19,8 @@ InstructionSet XExample extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for CV_MAXU: (select (i32 (setcc (i32 GPR:$rs1), (i32 GPR:$rs2), SETUGT)), GPR:$rs1, GPR:$rs2)
// CHECK-RV64-NEXT: Pattern for CV_MAXU: (select (i64 (setcc (i64 GPR:$rs1), (i64 GPR:$rs2), SETUGT)), GPR:$rs1, GPR:$rs2)
// CHECK-RV32-NEXT: Pattern for CV_MAXU [cv.maxu]: (select (i32 (setcc (i32 GPR:$rs1), (i32 GPR:$rs2), SETUGT)), GPR:$rs1, GPR:$rs2)
// CHECK-RV64-NEXT: Pattern for CV_MAXU [cv.maxu]: (select (i64 (setcc (i64 GPR:$rs1), (i64 GPR:$rs2), SETUGT)), GPR:$rs1, GPR:$rs2)
CV_MAXU {
encoding: 7'b0101110 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
Expand All @@ -31,8 +31,8 @@ InstructionSet XExample extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for NAND: (xor (and GPR:$rs2, GPR:$rs1), (i32 -1))
// CHECK-RV64-NEXT: Pattern for NAND: (xor (and GPR:$rs2, GPR:$rs1), (i64 -1))
// CHECK-RV32-NEXT: Pattern for NAND [nand]: (xor (and GPR:$rs2, GPR:$rs1), (i32 -1))
// CHECK-RV64-NEXT: Pattern for NAND [nand]: (xor (and GPR:$rs2, GPR:$rs1), (i64 -1))
NAND {
encoding: 7'b0101110 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1101011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
Expand All @@ -43,8 +43,8 @@ InstructionSet XExample extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for ADD3: (add (add GPR:$rs2, GPR:$rs1), GPR:$rd)
// CHECK-RV64-NEXT: Pattern for ADD3: (add (add GPR:$rs2, GPR:$rs1), GPR:$rd)
// CHECK-RV32-NEXT: Pattern for ADD3 [add3]: (add (add GPR:$rs2, GPR:$rs1), GPR:$rd)
// CHECK-RV64-NEXT: Pattern for ADD3 [add3]: (add (add GPR:$rs2, GPR:$rs1), GPR:$rd)
ADD3 {
encoding: 7'b1 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
assembly:"{name(rd)}, {name(rs2)}({name(rs1)})";
Expand Down
6 changes: 3 additions & 3 deletions core_descs/ExampleMemory.core_desc
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Expand Up @@ -2,7 +2,7 @@
// RUN: pattern-gen %s -O 3 --no-extend --mattr=+m --riscv-xlen 64 | FileCheck --check-prefixes=CHECK-RV64,CHECK-RV64-NOEXTED -allow-unused-prefixes %s


// CHECK-RV64: Pattern for LDR: (i64 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 (shl (i64 GPR:$rs2), (i64 (i64 uimm5:$imm)))))))))
// CHECK-RV64: Pattern for LDR [ldr]: (i64 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 (shl (i64 GPR:$rs2), (i64 (i64 uimm5:$imm)))))))))
LDR {
encoding: 2'b0 :: imm[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
assembly:"{name(rd)}, {imm} {name(rs2)}({name(rs1)})";
Expand All @@ -13,7 +13,7 @@ LDR {
}
}

// CHECK-RV64: Pattern for STR: (store (XLenVT GPR:$rs3), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 (shl (i64 GPR:$rs2), (i64 (i64 uimm5:$imm))))))))
// CHECK-RV64: Pattern for STR [str]: (store (XLenVT GPR:$rs3), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 (shl (i64 GPR:$rs2), (i64 (i64 uimm5:$imm))))))))
STR {
encoding: 2'b1 :: rs3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm[4:0] :: 7'b0000011;
assembly:"{name(rs3)}, {imm} {name(rs2)}({name(rs1)})";
Expand All @@ -23,7 +23,7 @@ STR {
}
}

// CHECK-RV64: Pattern for LOADMAC: (add GPR:$rd, (mul (i64 (load GPR:$rs2)), (i64 (load GPR:$rs1))))
// CHECK-RV64: Pattern for LOADMAC [loadmac]: (add GPR:$rd, (mul (i64 (load GPR:$rs2)), (i64 (load GPR:$rs1))))
LOADMAC {
encoding: 7'd40 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
assembly:"{name(rd)}, ({name(rs2)}), ({name(rs1)})";
Expand Down
16 changes: 8 additions & 8 deletions core_descs/ExampleRV32.core_desc
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Expand Up @@ -5,7 +5,7 @@ InstructionSet XExampleRV32 extends RISCVBase {

instructions {

// CHECK-RV32: Pattern for LB: (i32 (sextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
// CHECK-RV32: Pattern for LB [lb]: (i32 (sextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
LB {
operands: {
unsigned<5> rd;
Expand All @@ -21,7 +21,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for LH: (i32 (sextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
// CHECK-RV32-NEXT: Pattern for LH [lh]: (i32 (sextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
LH {
operands: {
unsigned<5> rd;
Expand All @@ -37,7 +37,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for LW: (i32 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
// CHECK-RV32-NEXT: Pattern for LW [lw]: (i32 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
LW {
operands: {
unsigned<5> rd;
Expand All @@ -53,7 +53,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for LBU: (i32 (zextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
// CHECK-RV32-NEXT: Pattern for LBU [lbu]: (i32 (zextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
LBU {
operands: {
unsigned<5> rd;
Expand All @@ -69,7 +69,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for LHU: (i32 (zextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
// CHECK-RV32-NEXT: Pattern for LHU [lhu]: (i32 (zextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
LHU {
operands: {
unsigned<5> rd;
Expand All @@ -85,7 +85,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for SB: (truncstorei8 (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
// CHECK-RV32-NEXT: Pattern for SB [sb]: (truncstorei8 (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
SB {
operands: {
unsigned<5> rs1;
Expand All @@ -100,7 +100,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for SH: (truncstorei16 (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
// CHECK-RV32-NEXT: Pattern for SH [sh]: (truncstorei16 (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
SH {
operands: {
unsigned<5> rs1;
Expand All @@ -115,7 +115,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for SW: (store (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
// CHECK-RV32-NEXT: Pattern for SW [sw]: (store (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
SW {
operands: {
unsigned<5> rs1;
Expand Down
10 changes: 5 additions & 5 deletions core_descs/ExampleRV32K.core_desc
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

InstructionSet XExampleRV32 extends RISCVBase {
instructions {
// CHECK-RV32: Pattern for K_LLI: (i32 uimm32:$imm)
// CHECK-RV32: Pattern for K_LLI [k.lli]: (i32 uimm32:$imm)
K_LLI {
encoding: 4'b0000 :: imm[31:0] :: rd[4:0] :: 7'b1011111;
assembly: {"k.lli", "{name(rd)}, {imm}"};
Expand All @@ -14,7 +14,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
X[rd] = (unsigned<XLEN>) ((unsigned) imm);
}
}
// CHECK-RV32: Pattern for K_ADDI: (add GPR:$rs1, (i32 uimm24:$imm))
// CHECK-RV32: Pattern for K_ADDI [k.addi]: (add GPR:$rs1, (i32 uimm24:$imm))
K_ADDI {
encoding: 4'b0001 :: imm[23:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011111;
assembly: {"k.addi", "{name(rd)}, {name(rs1)}, {imm}"};
Expand All @@ -25,7 +25,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}
}
// CHECK-RV32: Pattern for K_ANDI: (and GPR:$rs1, (i32 uimm24:$imm))
// CHECK-RV32: Pattern for K_ANDI [k.andi]: (and GPR:$rs1, (i32 uimm24:$imm))
K_ANDI {
encoding: 4'b0001 :: imm[23:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011111;
assembly: {"k.andi", "{name(rd)}, {name(rs1)}, {imm}"};
Expand All @@ -36,7 +36,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}
}
// CHECK-RV32: Pattern for K_XORI: (xor GPR:$rs1, (i32 uimm24:$imm))
// CHECK-RV32: Pattern for K_XORI [k.xori]: (xor GPR:$rs1, (i32 uimm24:$imm))
K_XORI {
encoding: 4'b0001 :: imm[23:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011111;
assembly: {"k.xori", "{name(rd)}, {name(rs1)}, {imm}"};
Expand All @@ -47,7 +47,7 @@ InstructionSet XExampleRV32 extends RISCVBase {
}
}
}
// CHECK-RV32: Pattern for K_ORI: (or GPR:$rs1, (i32 uimm24:$imm))
// CHECK-RV32: Pattern for K_ORI [k.ori]: (or GPR:$rs1, (i32 uimm24:$imm))
K_ORI {
encoding: 4'b0001 :: imm[23:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1011111;
assembly: {"k.ori", "{name(rd)}, {name(rs1)}, {imm}"};
Expand Down
24 changes: 12 additions & 12 deletions core_descs/ExampleRV64.core_desc
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Expand Up @@ -13,7 +13,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
// X[rd] = (signed<64>)res;
// }
// }
// CHECK-RV64: Pattern for ADDW2: (i64 (sext (i32 (add (i32 GPR:$rs2), (i32 GPR:$rs1)))))
// CHECK-RV64: Pattern for ADDW2 [addw2]: (i64 (sext (i32 (add (i32 GPR:$rs2), (i32 GPR:$rs1)))))
ADDW2 {
encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0111011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
Expand All @@ -22,7 +22,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
X[rd] = (signed<64>)res;
}
}
// CHECK-RV64-NEXT: Pattern for ADDW3: (i64 (sext (i32 (add (i32 GPR:$rs2), (i32 GPR:$rs1)))))
// CHECK-RV64-NEXT: Pattern for ADDW3 [addw3]: (i64 (sext (i32 (add (i32 GPR:$rs2), (i32 GPR:$rs1)))))
ADDW3 {
encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0111011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
Expand All @@ -32,7 +32,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for LB: (i64 (sextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
// CHECK-RV64-NEXT: Pattern for LB [lb]: (i64 (sextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
LB {
operands: {
unsigned<5> rd;
Expand All @@ -48,7 +48,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for LH: (i64 (sextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
// CHECK-RV64-NEXT: Pattern for LH [lh]: (i64 (sextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
LH {
operands: {
unsigned<5> rd;
Expand All @@ -64,7 +64,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for LW: (i64 (sextloadi32 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
// CHECK-RV64-NEXT: Pattern for LW [lw]: (i64 (sextloadi32 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
LW {
operands: {
unsigned<5> rd;
Expand All @@ -80,7 +80,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for LD: (i64 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
// CHECK-RV64-NEXT: Pattern for LD [ld]: (i64 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
LD {
operands: {
unsigned<5> rd;
Expand All @@ -96,7 +96,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for LBU: (i64 (zextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
// CHECK-RV64-NEXT: Pattern for LBU [lbu]: (i64 (zextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
LBU {
operands: {
unsigned<5> rd;
Expand All @@ -112,7 +112,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for LHU: (i64 (zextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
// CHECK-RV64-NEXT: Pattern for LHU [lhu]: (i64 (zextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
LHU {
operands: {
unsigned<5> rd;
Expand All @@ -128,7 +128,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for LWU: (i64 (zextloadi32 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
// CHECK-RV64-NEXT: Pattern for LWU [lwu]: (i64 (zextloadi32 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm))))))
LWU {
operands: {
unsigned<5> rd;
Expand All @@ -144,7 +144,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for SB: (truncstorei8 (XLenVT (i32 (trunc GPR:$rs2))), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm)))))
// CHECK-RV64-NEXT: Pattern for SB [sb]: (truncstorei8 (XLenVT (i32 (trunc GPR:$rs2))), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm)))))
SB {
operands: {
unsigned<5> rs1;
Expand All @@ -159,7 +159,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for SH: (truncstorei16 (XLenVT (i32 (trunc GPR:$rs2))), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm)))))
// CHECK-RV64-NEXT: Pattern for SH [sh]: (truncstorei16 (XLenVT (i32 (trunc GPR:$rs2))), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm)))))
SH {
operands: {
unsigned<5> rs1;
Expand All @@ -174,7 +174,7 @@ InstructionSet XExampleRV64 extends RISCVBase {
}
}

// CHECK-RV64-NEXT: Pattern for SW: (truncstorei32 (XLenVT (i32 (trunc GPR:$rs2))), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm)))))
// CHECK-RV64-NEXT: Pattern for SW [sw]: (truncstorei32 (XLenVT (i32 (trunc GPR:$rs2))), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 simm12:$imm)))))
SW {
operands: {
unsigned<5> rs1;
Expand Down
8 changes: 4 additions & 4 deletions core_descs/ExampleXCV.core_desc
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Expand Up @@ -5,7 +5,7 @@ InstructionSet XExampleCoreV extends RISCVBase {

instructions {

// CHECK-RV32: Pattern for CV_MAC: (add (mul GPR:$rs2, GPR:$rs1), GPR:$rd)
// CHECK-RV32: Pattern for CV_MAC [cv.mac]: (add (mul GPR:$rs2, GPR:$rs1), GPR:$rd)
CV_MAC {
encoding: 7'b1001000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
Expand All @@ -15,7 +15,7 @@ InstructionSet XExampleCoreV extends RISCVBase {
}
}

// CHECK-RV32-NEXT: Pattern for CV_ABS: (xor (add GPR:$rs1, (i32 (sra (i32 GPR:$rs1), (i32 (i32 31))))), (i32 (sra (i32 GPR:$rs1), (i32 (i32 31)))))
// CHECK-RV32-NEXT: Pattern for CV_ABS [cv.abs]: (xor (add GPR:$rs1, (i32 (sra (i32 GPR:$rs1), (i32 (i32 31))))), (i32 (sra (i32 GPR:$rs1), (i32 (i32 31)))))
CV_ABS {
encoding: 7'b0101000 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: "{name(rd)}, {name(rs1)}";
Expand All @@ -26,8 +26,8 @@ InstructionSet XExampleCoreV extends RISCVBase {
}
}

// CHECK-RV32-EXTEND-NEXT: Pattern for CV_ADDN: (select (i32 (setcc (i32 (i32 uimm5:$Luimm5)), (i32 (i32 0)), SETEQ)), (add GPR:$rs2, GPR:$rs1), (select (i32 (setcc (i32 (i32 uimm5:$Luimm5)), (i32 (i32 32)), SETULT)), (or (i32 (srl (i32 (add GPR:$rs2, GPR:$rs1)), (i32 (i32 uimm5:$Luimm5)))), (i32 (shl (i32 (i32 (sra (i32 (i32 (shl (i32 (add (i32 (setcc (i32 (add GPR:$rs2, GPR:$rs1)), (i32 GPR:$rs1), SETULT)), (i32 0))), (i32 (i32 31))))), (i32 (i32 31))))), (i32 (sub (i32 32), (i32 uimm5:$Luimm5)))))), (i32 (sra (i32 (i32 (sra (i32 (i32 (shl (i32 (add (i32 (setcc (i32 (add GPR:$rs2, GPR:$rs1)), (i32 GPR:$rs1), SETULT)), (i32 0))), (i32 (i32 31))))), (i32 (i32 31))))), (i32 (sub (i32 uimm5:$Luimm5), (i32 32)))))))
// CHECK-RV32-NOEXTEND-NEXT: Pattern for CV_ADDN: (i32 (sra (i32 (add GPR:$rs2, GPR:$rs1)), (i32 (i32 uimm5:$Luimm5))))
// CHECK-RV32-EXTEND-NEXT: Pattern for CV_ADDN [cv.addn]: (select (i32 (setcc (i32 (i32 uimm5:$Luimm5)), (i32 (i32 0)), SETEQ)), (add GPR:$rs2, GPR:$rs1), (select (i32 (setcc (i32 (i32 uimm5:$Luimm5)), (i32 (i32 32)), SETULT)), (or (i32 (srl (i32 (add GPR:$rs2, GPR:$rs1)), (i32 (i32 uimm5:$Luimm5)))), (i32 (shl (i32 (i32 (sra (i32 (i32 (shl (i32 (add (i32 (setcc (i32 (add GPR:$rs2, GPR:$rs1)), (i32 GPR:$rs1), SETULT)), (i32 0))), (i32 (i32 31))))), (i32 (i32 31))))), (i32 (sub (i32 32), (i32 uimm5:$Luimm5)))))), (i32 (sra (i32 (i32 (sra (i32 (i32 (shl (i32 (add (i32 (setcc (i32 (add GPR:$rs2, GPR:$rs1)), (i32 GPR:$rs1), SETULT)), (i32 0))), (i32 (i32 31))))), (i32 (i32 31))))), (i32 (sub (i32 uimm5:$Luimm5), (i32 32)))))))
// CHECK-RV32-NOEXTEND-NEXT: Pattern for CV_ADDN [cv.addn]: (i32 (sra (i32 (add GPR:$rs2, GPR:$rs1)), (i32 (i32 uimm5:$Luimm5))))
CV_ADDN {
encoding: 2'b00 :: Luimm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}, {Luimm5}";
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