Center the agent thesis and define a controlled Agent Task Proof

AGENTS.md

@@ -25,6 +25,7 @@ If blocked, pick the simplest viable default, record it in `DECISIONS.md`, and m
 
 ## Active track
 - **Now:** S12.4 HIL appliance v0 physical loop (serial observer first, then power/reset actuation), feeding the preferred appliance-mediated S13 metal HIL graduation path. Standalone golden-machine `PASS/METAL` must be provenance-stamped separately. S14 USB xHCI + HID is deferred to a design pass.
+- **Parallel software lane:** SW0 Agent Task Proof Phase A can start independently of physical H0–H3; it does not wait for NVMe graduation. S14 prerequisites from both lanes live in `NEXT_TASKS.md`.
 - **Authoritative pair:** `CURRENT_STATUS.md` + `NEXT_TASKS.md` (deferred decisions in `ROADMAP.md` §13). `SLICES.md` has slice history.
 - **Keep green:** `just s11`, `just s12`, `just s13`, and `just foundry-org-governance-g0` when touching org/research planning.
 

CHANGELOG.md

@@ -3,6 +3,24 @@
 ## [Unreleased]
 
 ### Changed
+- Revised the Agent Task Proof to separate Linux scoped shell, Linux typed, and
+  RamenOS typed effects using a shared typed protocol and hidden fixture bank.
+  Defined canonical authority envelopes/probes, a pilot-to-powered-study rule,
+  and separate completion, authority, cost, and audit/replay claims.
+- Marked Platform Overview components as Landed, Partial, or Target architecture;
+  separated the H0–H3 physical queue from SW0 software work and made S14 depend
+  on the relevant evidence from both lanes. GitHub description refresh is queued
+  for after merge. No experiment, target-enforcement, or hardware claim is added.
+- Updated the appliance gate's queue-label assertion from P0/P3 to H0/H3 while
+  preserving its requirement that serial observation precede S13 graduation.
+- Reframed the public README around the agent interaction problem and documented
+  host, QEMU, simulation, and hardware boundaries. Moved operator details and
+  Store examples into `docs/DEVELOPMENT_REFERENCE.md`, refreshed contributor
+  gates, and corrected claims about coding-agent hooks.
+- Planned an Agent Task Proof before S14 expansion: scoped configuration repair,
+  validator execution, forced unauthorized calls, audit/replay, and a matched
+  Linux comparison. S12.4/S13 physical execution order remains intact. This is
+  a plan, not an executable demo or a measured agent-advantage result.
 - Enforced the WASM SDK's signed output capacity before bridge operations and
   before copying replies, including fixed IDL reply sizes and raw shared-memory
   reads. Added adjacent-sentinel, malformed-capacity, side-effect-preflight, and

CURRENT_STATUS.md

@@ -3,6 +3,7 @@
 **Last Updated:** 2026-09-16
 **Status:** Active and authoritative for landed state
 **Current Slice:** S12.4 HIL appliance v0 physical loop
+**Software Lane:** SW0 Agent Task Proof — planned; Phase A is the next software action
 
 ## Active Execution Track
 
@@ -11,9 +12,15 @@ then Intel AMT 11 power/reset actuation. Once that loop is stable, the preferred
 HIL graduation path runs through the appliance on Tier-1 or lab hardware.
 Standalone golden-machine graduation remains a distinct `PASS/METAL` path only
 when per-gate evidence stamps `claim_path: operator-golden-machine`. S14 USB
-xHCI and HID stays deferred until the appliance loop is proven.
+xHCI and HID stays deferred until the H0/H1 appliance loop is proven, SW0 Phase
+A/B results are reviewed, and its own design/IDL/Oracle/gate prerequisites land.
 
-The next executable step is maintained in [NEXT_TASKS.md](NEXT_TASKS.md).
+H0–H3 name the physical queue. SW0 is an independent software queue and can
+start now without waiting for NVMe graduation. Its current deliverable is a
+plan; no Agent Task Proof implementation or comparison has landed. These labels
+do not allocate new slice numbers or change governance authority.
+
+The next action in each lane is maintained in [NEXT_TASKS.md](NEXT_TASKS.md).
 Medium-range sequencing and deferred decisions live in [ROADMAP.md](ROADMAP.md).
 
 ## Evidence Boundary
@@ -24,6 +31,7 @@ Medium-range sequencing and deferred decisions live in [ROADMAP.md](ROADMAP.md).
 | S12 golden machine | QEMU probes and HIL gate scaffolds landed | Appliance-mediated live capture and physical graduation |
 | S13 storage | QEMU Oracle, replay, and runtime block I/O landed | Live NVMe boot plus two-boot atomic rollback evidence |
 | S12.4 appliance | Manifest, evidence schema, gate, serial-observer scaffold, and physical wiring landed | First live serial capture, then provisioned and validated AMT control |
+| Agent Task Proof (SW0) | Plan only; host Semantic State, Store, runner, and selected QEMU bridges exist separately | Three-arm task integration, protocol/authority mapping checks, denial/replay gate, powered model comparison, and task-specific target enforcement |
 | G0 RamenOrg | Governance schemas, packets, validators, trials, and gate landed | Research packets and stronger identity-level role separation |
 
 `PASS/QEMU` is not metal evidence. `PASS/HIL-LOG`, `PASS/HIL-LIVE`,
@@ -32,6 +40,21 @@ see [EVIDENCE_LEVELS.md](EVIDENCE_LEVELS.md).
 
 ## Landed Milestones
 
+### Agent-facing proof plan and public docs (2026-09-16)
+
+- Public entry points now lead with the agent interaction problem and distinguish
+  host services, selected QEMU paths, simulation, and pending hardware evidence.
+- The [Agent Task Proof plan](docs/plans/2026-09-16-agent-task-proof.md) specifies
+  Linux scoped shell, Linux typed, and RamenOS typed arms, a shared typed protocol,
+  canonical authority manifests, forced backend probes, and separate completion,
+  authority, cost, and audit/replay claims. Pilot estimates feed a predeclared
+  power calculation; final evaluation uses held-out fixtures. None of those runs
+  has occurred yet.
+- [Platform Overview](PLATFORM_OVERVIEW.md) now marks components as Landed,
+  Partial, or Target architecture. H0–H3 and SW0 are independent execution lanes.
+- This milestone is documentation and planning only. No executable task proof,
+  measured agent advantage, new enforcement path, or physical result has landed.
+
 ### Memory, native runner, and Store review fixes (2026-09-16)
 
 - Shared-memory allocation clears full backing frames, including partial-page
@@ -117,6 +140,9 @@ is [docs/plans/2026-06-23-research-backed-ramenorg.md](docs/plans/2026-06-23-res
 
 ## Known Gaps
 
+- No end-to-end Agent Task Proof or measured comparison with shell/tool agents.
+- Native runner, Store, and Semantic State reactor remain host-side; default
+  snapshot metadata includes placeholders, and execution-fabric routing is simulated.
 - No `PASS/METAL` claim for S12 or S13 yet.
 - S13 atomic rollback still needs the complete two-boot physical protocol.
 - S14 interactivity has no approved implementation plan.

NEXT_TASKS.md

@@ -6,23 +6,30 @@
 > [CURRENT_STATUS.md](CURRENT_STATUS.md) records what landed. This file records
 > what to execute next. [ROADMAP.md](ROADMAP.md) is directional, not operational.
 
-## Active Execution Track
+## Parallel Execution Lanes
 
-**Now:** Run the first live HIL appliance serial capture on the physically ready Pi↔M900
-chain, then provision and validate the M900's Intel AMT 11 power/reset path.
+**Now:** H0 HIL appliance serial observer — first live capture — and SW0 Agent Task Proof Phase A can proceed independently.
+
+H0–H3 are ordered within the physical lane; SW0 is an independent software lane,
+not the next item after H3. Start SW0 now without waiting for lab access or NVMe
+graduation. Lane labels are queue positions, not new slice identifiers.
+
+## Physical Lane: H0–H3
+
+Run the first live capture on the physically ready Pi↔M900 chain, then provision
+and validate the M900's Intel AMT 11 power/reset path.
 S12 runs on the installed 240 GB SanDisk SATA SSD. Add a compatible M.2 2280
 PCIe NVMe drive before S13 metal graduation. Front-panel relays and a
 smart plug/PDU remain deferred until AMT testing shows they are necessary.
 
-| Priority | Task | Completion signal |
+| Order | Task | Completion signal |
 |----------|------|-------------------|
-| P0 | S12.4.1 HIL appliance serial observer — first live capture | `RAMEN_HIL_APPLIANCE=1 RAMEN_HIL_SERIAL_DEV=/dev/ttyUSB0 just hil-appliance` captures live serial and emits valid controller evidence |
-| P1 | S12.4.2 Intel AMT power/reset actuator | AMT status, power-on, power-off, reset, and power-cycle are validated from the Pi and represented in controller evidence JSON |
-| P2 | S12 physical graduation on the installed SanDisk SATA SSD | `RAMEN_HIL_APPLIANCE=1 RAMEN_HIL_GOLDEN_MACHINE=1 just s12-hil` produces valid live provenance |
-| P3 | Add M.2 2280 PCIe NVMe and run S13 metal graduation | `RAMEN_HIL_APPLIANCE=1 RAMEN_HIL_GOLDEN_MACHINE=1 RAMEN_HIL_GRADUATION=1 just s13-hil` produces valid live provenance with `claim_path: appliance-mediated` |
-| P4 | S14 USB xHCI and HID design pass | Approved short plan, IDL boundary, and Foundry gate definition before implementation |
+| H0 | S12.4.1 HIL appliance serial observer — first live capture | `RAMEN_HIL_APPLIANCE=1 RAMEN_HIL_SERIAL_DEV=/dev/ttyUSB0 just hil-appliance` captures live serial and emits valid controller evidence |
+| H1 | S12.4.2 Intel AMT power/reset actuator | AMT status, power-on, power-off, reset, and power-cycle are validated from the Pi and represented in controller evidence JSON |
+| H2 | S12 physical graduation on the installed SanDisk SATA SSD | `RAMEN_HIL_APPLIANCE=1 RAMEN_HIL_GOLDEN_MACHINE=1 just s12-hil` produces valid live provenance |
+| H3 | Add M.2 2280 PCIe NVMe and run S13 metal graduation | `RAMEN_HIL_APPLIANCE=1 RAMEN_HIL_GOLDEN_MACHINE=1 RAMEN_HIL_GRADUATION=1 just s13-hil` produces valid live provenance with `claim_path: appliance-mediated` |
 
-### P0 Acceptance Criteria
+### H0 Acceptance Criteria
 
 - `tools/hil/appliance_capture_serial.sh` captures from the configured appliance
   serial device without accepting stale graduation logs.
@@ -42,7 +49,7 @@ For graduation, set a unique `RAMEN_HIL_RUN_ID`, `RAMEN_HIL_APPLIANCE_ID`, and
 boot. Use a fresh nonce for each boot and run the individual physical gates when
 manual media/nonce staging is needed. See [EVIDENCE_LEVELS.md](EVIDENCE_LEVELS.md).
 
-### P1 Acceptance Criteria
+### H1 Acceptance Criteria
 
 - Provision AMT 11 through MEBx on a trusted wired lab network.
 - Add AMT-backed status, power-on, power-off, reset, and power-cycle commands.
@@ -54,9 +61,45 @@ manual media/nonce staging is needed. See [EVIDENCE_LEVELS.md](EVIDENCE_LEVELS.m
 - Physical actuation remains opt-in; governance scaffolding grants no ambient
   HIL actuation authority.
 
+## Software Lane: SW0 Agent Task Proof
+
+**Next software action:** write Phase A's deterministic task, control-protocol,
+authority-mapping, denial, and replay assertions, then implement the adapters.
+SW0 has no H0–H3 prerequisite. The
+[Agent Task Proof plan](docs/plans/2026-09-16-agent-task-proof.md) defines one
+consumer task: repair a scoped configuration, execute its pinned validator, and
+report the resulting artifact while access to another workspace is denied.
+
+1. Inventory the actual Semantic State, Store, broker, and native runner paths.
+   Write the task-success, forced-denial, revocation, conflict, audit, and replay
+   assertions first; define missing native operations through IDL/codegen.
+2. Implement the fixture and scripted consumer across the host service boundary.
+   Ship a deterministic Foundry gate and inspectable evidence bundle. Report
+   host enforcement explicitly; no target-native or comparative claim yet.
+3. Pilot Linux scoped shell, Linux typed, and RamenOS typed using one evaluator
+   and hidden fixture bank. Verify LT/RT protocol equivalence and canonical
+   authority mappings. Use the predeclared power rule to size and freeze the
+   final comparison, then run it opt-in. Report the three contrasts and separate
+   completion, authority, cost, and audit/replay outcomes, including uncertainty.
+4. Add target-side enforcement evidence for named task operations. The existing
+   QEMU snapshot/IPC bridge alone cannot establish this task's OS boundary.
+
+The proof and its proposed commands are **not implemented**. Completion of the
+plan is not completion of the experiment; an unfavorable comparison is a valid
+result and should inform the next software slice.
+
+## S14 Expansion Prerequisites
+
+S14 USB xHCI/HID implementation depends on both lanes: a demonstrated stable
+H0/H1 observation-and-actuation loop, and review of SW0 Phase A evidence and
+Phase B comparison results. It also needs its own short design, Reference Vault
+and Oracle trace, IDL boundary, and Foundry gate definition before implementation.
+H2/H3 remain the physical graduation sequence; they do not block SW0. SW0 Phase C
+is a separate target-enforcement follow-up, not a prerequisite for the host study.
+
 ## Parallel Project-Control Track
 
-This lane can proceed without displacing P0-P4.
+This lane can proceed without displacing H0–H3 or SW0.
 
 | Priority | Task | Gate or artifact |
 |----------|------|------------------|
@@ -84,7 +127,11 @@ before pushing when practical.
 
 ## Deferred
 
-- S14 implementation until the appliance loop is stable and a design pass lands.
+- S14 implementation until the H0/H1 loop is stable, SW0 Phase A/B results are
+  reviewed, and the S14 design/IDL/Oracle/gate prerequisites above are met.
+- After this branch merges, update the GitHub repository description to:
+  "An experimental Rust OS for agents: typed capabilities, machine-readable
+  system state, and evidence-gated hardware support."
 - Smart plug/PDU and front-panel relay purchases until AMT validation establishes
   a concrete recovery gap.
 - Full execution-fabric transport and broad real-kernel broker migration.