Senior Digital Design Engineer with focus on ASIC and FPGA development. I build reusable RTL libraries, design toolkits, and IP cores in SystemVerilog and Verilog.
| Repository | Description |
|---|---|
| fpga-design-toolkit | FPGA design toolkit with templates and standard modules |
| asic-desing-toolkit | ASIC design toolkit with templates and open-source PDKs |
| cdc_lib | Clock Domain Crossing (CDC) modules for Digital designs |
| clk_lib | Clock divider library — multiple architectures and methods |
| spi-config-interface | Configuration register file accessed via SPI |
| MEM_lib | SystemVerilog memory interface library |
| dff-interactive | Interactive D flip-flop web demo |
- RTL design and micro-architecture in SystemVerilog / Verilog
- Clock Domain Crossing (CDC) design and formal verification
- Memory interface design and protocol implementation
- Logic synthesis, static timing analysis, and timing closure
- Functional simulation and verification flows
Open Source: Yosys · OpenROAD · OpenLane · Verilator · Icarus Verilog · GTKWave
Commercial: Vivado · Quartus · ModelSim · Synopsys DC · VCS · PrimeTime · Verdi
Email: moaazkh96@gmail.com LinkedIn: https://www.linkedin.com/in/moaaz-k-fraize/