SIMD playground

[mosra]

Right now this is rather an experiment investigating possibilities of integrating SIMD-enabled algorithms into the math library. Currently there's the simplest algorithms ever, packing and unpacking index arrays to larger/smaller representations (and I was not able to beat the compiler, my AVX2 version was as what GCC managed to optimize out of the scalar implementation). It also shows how GCC function multi-versioning could be used to have multiple implementations in the same binary instead of compiling always only for one target.

CPU feature detection and dispatch were moved to mosra/corrade#115, the following list contains just the remaining tasks related to actual SIMD code:

• make the algorithms behave properly with "leftovers" (not a full block of 16 elements at the end)
• investigate benefits of GCC- and Clang-specific vector extensions for easier basic ops on SIMD vectors
• investigate perf effects of aligned/unaligned loads and stores (this is where it could be possible to beat the compiler, if I force the input data to be aligned)
• investigate possible slowdowns due to accidental leftovers in AVX registers
• investigate differences in intrinsics on MSVC vs GCC not that many based on practical experience with tests in Compile-time and runtime CPU feature (SIMD) detection and dispatch corrade#115
• look into ARM NEON for these simple cases
  • Travis has ARM builds now: https://blog.travis-ci.com/2019-10-07-multi-cpu-architecture-support Travis is dead, having a CircleCI ARM build instead
• Emscripten and SIMD -- https://emscripten.org/docs/porting/simd.html
  • useful: https://github.com/zeux/wasm-simd
• have an ISPC implementation as a baseline
• https://github.com/nemequ/simde is a neat thing for testing
• and https://www.officedaytime.com/simd512e/ for documentation
• figure out how to compile functions for different targets -- on GCC we need -m<arch> in order to be able to use the intrinsics at all -- resolved in Compile-time and runtime CPU feature (SIMD) detection and dispatch corrade#115
  • on MSVC we can build w/ /arch:SSE2 and use all SSE3–SSE4.2 intrinsics, then /arch:AVX for all AVX1 code etc, which reduces the combinations a lot; technically one can use
  • separate compile unit per file could work when everything else fails but adds a ton of extra build targets
  • GCC has a target attribute that could solve this -- what's the support on 4.8? what about clang? alternatives on msvc?

    void foo(Simd::Sse2) __attribute__ ((__target__ ("sse2")));
    void foo(Simd::Avx2) __attribute__ ((__target__ ("avx2")));

  • may need to do NEVER_INLINE on runtime dispatchers so LTO + speculative execution doesn't cause SIGILL? https://www.reddit.com/r/cpp/comments/eneib0/detecting_sse_features_at_runtime/fed6zvr?utm_source=share&utm_medium=web2x&context=3 -- investigate further, might be avoidable with the target attributes
  • template code from files compiled with different flags may get mixed up, causing ODR violations or again SIGILL if a wrong variant gets chosen by the linker -- https://www.reddit.com/r/cpp/comments/eneib0/detecting_sse_features_at_runtime/fdzqbqg?utm_source=share&utm_medium=web2x&context=3 -- avoid templates in that code? again might be avoidable with the target attributes

Useful SIMD-able things to add

List will grow.

• stuff from https://github.com/komrad36/FastArrayOps
• less crappy cross-product: http://fastcpp.blogspot.com/2011/04/vector-cross-product-using-sse-code.html
• sin/cos optimizations: http://gruntthepeon.free.fr/ssemath/ ... is there anything newer? builtins?
• 💯 MeshTools::generateSmoothNormals() / generateFlatNormals(), nicely self-contained and could have a big visible impact
• optimized min/max on a strided 3D float/byte/... view, specialize for the last two dimensions being contiguous and the last dimension being 1/2/3/4 elements, for quick detection of single-color images -- for 3 elements it needs to go in batches of 12/24/48 values (i.e., 3 128/256/512 vectors) to avoid mixing up different components
  • http://0x80.pl/notesen/2018-10-03-simd-index-of-min.html (don't need argmin, just min)
  • https://github.com/schombert/Open-V2/blob/master/concurrency_tools/vectorized_min_max.cpp
• SIMD-enabled Utility::copy() (lots of potential for optimizations when the (sub)ranges are contiguous or evenly spaced)
• In-place image flip / array reversal -- https://dev.to/wunk/fast-array-reversal-with-simd-j3p
• Batch float (un)packing
• Batch half-float (un)packing -- ryg has SIMD-enabled half->float variants on https://gist.github.com/rygorous/2144712, implement them? is there also float->half? (might obsolete what was done in Math: table-based half-float packing/unpacking. #275)
  • actually, there's an intrisnic for this: https://walbourn.github.io/directxmath-f16c-and-fma/
  • and for ARM too: https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=float16
  • https://github.com/Maratyszcza/FP16
• Batch two-dimensional FMA for combining two images
• RGB <-> RGBA, both 8 and 16bit, needed by Vulkan
• transformation matrix hierarchy calculation (linear array with backreferences to parents, optionally masked), specialized for 4x4, 3x4, 3x3, 3x2; what about quats etc?
  • https://codereview.stackexchange.com/questions/177616/avx-simd-in-matrix-multiplication
  • https://codereview.stackexchange.com/questions/181342/fast-affine-transformations-of-many-3d-points-by-one-3%C3%974-matrix?rq=1
• And then batch cofactor / normal matrix calculation for all transformation matrices https://codereview.stackexchange.com/questions/225652/4%C3%974-cofactor-in-sse
• Containers::BoolArray, popcnt and other operations
  • hand-written code might be faster than the instruction!? http://danluu.com/assembly-intrinsics/, https://news.ycombinator.com/item?id=11277891
• AVX/AVX512 AABB intersection: https://twitter.com/ChrisGr93091552/status/1483135959596081153
  • also https://github.com/bryanmcnett/aabo
• RGB32F -> RGB8Srgb -- https://gist.github.com/rygorous/2203834 (also check the comment below)
• image downsampling (ispc version: https://github.com/Traverse-Research/ispc-downsampler/blob/main/src/ispc/kernels/lanczos3.ispc)

[codecov-io]

Codecov Report

Merging #306 into master will not change coverage.
The diff coverage is n/a.

@@           Coverage Diff           @@
##           master     #306   +/-   ##
=======================================
  Coverage   53.11%   53.11%           
=======================================
  Files         324      324           
  Lines       16661    16661           
=======================================
  Hits         8850     8850           
  Misses       7811     7811

Impacted Files	Coverage Δ
src/Magnum/Math/Packing.h	100% <ø> (ø)	⬆️

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[mosra]

Compile-time and runtime CPU feature detection APIs were moved to Corrade, as it makes more sense for them to live there. There's still a few unresolved design / implementation issues so it's in a draft PR for now: mosra/corrade#115