Releases: mrbya/dvm
Releases · mrbya/dvm
dvm 1.3.1
dvm v1.3.0
Added features:
- C code compilation and linking using DPI
- SystemVerilog module template generation
- pure SystemVerilog simulation
- coverage report generation
- coverage dashboard wrapper
dvm v1.2.0
Added script arguments to control:
- compile list
- testbench timescale
- testbench snapshot for both elaboration and simulation
- testbench topmodule
- uvm verbosity control for simulation
without the need to modify the DVM project config
dvm v1.1.1
- minor bug fixes
- added options to overwrite specific config values during
-comp,-elab,-sim, and-run(refer to script-helpfor more info)
dvm v1.1.0
features added
- Batch mode
- output log control
dvm v1.0.0
DVM release v1.0.0
features
- DVM project management
- xvlog compilation
- xelab elaboration
- xsim simulation
- waveform dump
- waveform preview using Vivado GUI