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vtoth2 edited this page Jan 6, 2024 · 7 revisions

DVM project

To manage a DVM project use the dvm script inside a DVM project directory.

For exact usage documentation of the script use dvm -help

New project

To create a new project under your current working directory use dvm -new=[PROJECT NAME] (Whitespaces in DVM project name are not allowed).

DVM will create a new directory with [PROJECT NAME] with all the required directories and config files.

Example:

[mycodes/vivado]$ dvm -new=best_rtl_project
Generating new DVM project: best_rtl_project
New project created.

[mycodes/vivado]$ cd best_rtl_project

[mycodes/vivado/best_rtl_project]$

Project configuration

DVM projects are configured by their dvmproject.conf config file located under ...path_to_project/dvm containing a Perl hash with the following data:

project

  • dir - DVM project directory path
  • dvmDir - DVM project output and config directory (under the DVM project and excluding the path to the project)
  • logDir - output logs directory (under DVM project config dir)

compilation

  • list - compile list for xvlog (compile list has to be located under the dvm config directory dvmDir)
  • logDir - xvlog compilation logs output dir (under project logDir; can be owerwritten using -complog option)
  • log - xvlog compilation log name (include path if you want to generate log outside DVM project dir)
  • args - list of additional arguments used during xvlog compilation (-L uvm arg configured by default)

dpi

  • list - C code compile list for xsc (compile list has to be located under the dvm config directory dvmDir)
  • logDir - xsc compilation logs output dir (under project logDir)
  • log - xsc compilation log name (include path if you want to generate log outside DVM project dir)
  • args - list of additional arguments used during xsc compilation

elaboration

  • tbTop - top module of the testbench (excluding file extension - default: [PROJECT NAME]_tb_top)
  • tbName - name of the testbench snapshot created during elaboration
  • timescale - timescale used for elaboration and simulation (default: 1ns/1ps)
  • logDir - xelab elaboration log directory (under project logDir; can be owerwritten using -elablog option)
  • log - xelab elaboration log name (include path if you want to generate log outside DVM project dir)
  • args - list of additional arguments used during xvlog compilation (-debug wave included when using -wave option)

simulation

  • logDir - xsim simulation log directory (under project logDir; can be owerwritten using -simlog option)
  • log - xsim simulation log name (include path if you want to generate log outside DVM project dir; use {{testname}} string in log name to generate based on simulation test name)
  • verbosity - UVM message verbosity (default: UVM_LOW)
  • defTest - default UVM test used by dvm -run (if not configured need to specify using the -test option)
  • batch - switch to run batch of UVM tests specified by a test list
  • testlist - file specifying a list of UVM tests to run (default configured by config file)
  • args - list of additional arguments used during xsim simulation (--tclbatch wfcfg.tcl included when using -wave option)

Config example

(
    'project'     => {
        'dir'       => 'C:/Users/viktor.toth/Desktop/This/mycodes/vivado/best_rtl_project',
        'dvmDir'    => 'dvm',
	'logDir'    => 'logs',
    },

    'compilation' => {
        'list'      => 'best_rtl_project_compile_list.f',
        'logDir'    => 'comp',
        'log'       => 'comp.log',
        'args'      => '-L uvm',
    },

    'dpi' => {
        'list'      => 'best_rtl_project_dpi_list.f',
        'logDir'    => 'dpi',
        'log'       => 'dpi.log',
        'args'      => ' ',
    },

    'elaboration' => {
        'tbTop'     => 'best_rtl_project_tb_top',
        'tbName'    => 'top',
        'timescale' => '1ns/1ps',
        'logDir'    => 'elab',
        'log'       => 'elab.log',
        'dpilib'    => 0
        'args'      => ' ',
    },

    'simulation'  => {
        'logDir'    => 'sim',
        'log'       => 'sim_{{testname}}.log',
        'verbosity' => 'UVM_LOW',
        'defTest'   => 'best_rtl_project_full_test',
        'batch'     =>  1,
        'testlist'  => 'best_rtl_project_test_list.f',
        'args'      => ' ',
    },
)

Project structure

DVM project
├───design
│   └───src                                 //HDL design sources
├───dvm
│   │   best_rtl_project_compile_list.f     //compile list for HDL design and verif sources
│   │   best_rtl_project_test_list.f        //list of uvm tests to run in batch mode
│   │   dvmproject.conf                     //DVM project config file
│   │   wfcfg.tcl                           //tcl script for waveform dump
│   │
│   └───logs
│       ├───comp
│       ├───dpi
│       ├───elab
│       └───sim
└───verif                                   //HDL verification sources
    ├───env
    │   ├───agents
    │   └───top
    ├───tb
    │   └───src
    │           best_rtl_project_tb_top.sv  //testbench top module
    │
    └───test
        ├───seq
        └───src

SystemVerilog module generation

To generate a sv module template use the -module option. This generates a module template under the default sesign source folder. You can specify the template folder using the -path option.

Project compilation

Compile project using dvm -comp

Example:

[mycodes/vivado/alu_uvm_test/dvm]$ dvm -comp
Loading DVM project config...
DVM project config loaded.
ECHO is off.
ECHO is off.
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/viktor.toth/Desktop/This/mycodes/vivado2/alu_uvm_test/design/src/alu.sv" into library work
INFO: [VRFC 10-311] analyzing module alu
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/viktor.toth/Desktop/This/mycodes/vivado2/alu_uvm_test/verif/env/agents/alu_agent/alu_agent_pkg.sv" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/viktor.toth/Desktop/This/mycodes/vivado2/alu_uvm_test/verif/env/ref_model/alu_ref_model_pkg.sv" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/viktor.toth/Desktop/This/mycodes/vivado2/alu_uvm_test/verif/env/top/alu_env_pkg.sv" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/viktor.toth/Desktop/This/mycodes/vivado2/alu_uvm_test/verif/test/seq/alu_seq_pkg.sv" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/viktor.toth/Desktop/This/mycodes/vivado2/alu_uvm_test/verif/test/src/alu_test_pkg.sv" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/viktor.toth/Desktop/This/mycodes/vivado2/alu_uvm_test/verif/tb/src/alu_uvm_test_tb_top.sv" into library work
INFO: [VRFC 10-311] analyzing module alu_uvm_test_tb_top

[mycodes/vivado/alu_uvm_test/dvm]$

Project elaboration

Elaborate project using dvm -elab

Example:

[mycodes/vivado/alu_uvm_test/dvm]$ dvm -elab
Loading DVM project config...
DVM project config loaded.
ECHO is off.
ECHO is off.
Vivado Simulator v2023.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe alu_uvm_test_tb_top -relax -s top -timescale 1ns/1ps -log elab.log
Multi-threading is on. Using 10 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4468] File : /proj/xbuilds/SWIP/9999.0_0820_0302/installs/lin64/Vivado/2024.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv, Line : 25994, RANDC variable size more than 8 bits. This will be treated as a RAND variable instead.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package work.alu_test_pkg
Compiling package uvm.uvm_pkg
Compiling package std.std
Compiling package work.alu_agent_pkg
Compiling package work.alu_ref_model_pkg
Compiling package work.alu_env_pkg
Compiling package work.alu_seq_pkg
Compiling module work.dr_cb
Compiling module work.rc_cb
Compiling module work.alu_interface
Compiling module work.alu
Compiling module work.alu_uvm_test_tb_top
Built simulation snapshot top

[mycodes/vivado/alu_uvm_test/dvm]$

Running simulation

Run simulation using dvm -run

Need to provide a UVM test using the -test option if a default UVM test is not configured.

Example:

[mycodes/vivado/alu_uvm_test/dvm]$ dvm -run
Loading DVM project config...
DVM project config loaded.
ECHO is off.
ECHO is off.

****** xsim v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source xsim.dir/top/xsim_script.tcl
# xsim {top} -testplusarg UVM_VERBOSITY=UVM_LOW -testplusarg UVM_TESTNAME=alu_test_cmp_short -autoloadwcfg -runall
Time resolution is 1 ps
run -all

***SIMULATION LOG***
.
.
.
***SIMULATION LOG***

$finish called at time : 2045 ns : File "C:\Xilinx\Vivado\2023.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv" Line 18699
exit
INFO: [Common 17-206] Exiting xsim at Sun Nov 26 23:27:22 2023...

[mycodes/vivado/alu_uvm_test/dvm]$

Full run

Compilation, elaboration and simulation steps can be executed in sequence using the -all option.

Waveform dump

DVM does not instruct xelab and xsim to dump waveforms by default. To dump simulation waveforms use the -wave option or configure the coresponding elaboration and simulation args in the DVM config file.

DVM -wave option dumps all waveforms into a .wdb database named after the testbench snapshot.

To subsequently view the waveforms start Vivado GUI using dvm -gui

Batch mode

DVM allows for a batch of UVM tests to be run using the -batch option or configuring the simulation batch switch in the config file.

In batch mode DVM runs a batch of UVM tests specified by a test list file configured in the config file or provided by the -testlist option.

Pure Systemverilog simulation

To run pure systemverilog simulation use the -runsv option. Using this options ignores UVM related settings configurend in DVM config file and options used.

DPI-C code

To compile C code used during simulation use the -dpi option. This uses a built in gcc compiler managed by VIVADO xsc tool to compile C code privided by the dpi compile list configured in the DVM config or provided by the -dpilist option.

To link the compiled object files to a testbench snapshot configure the dpilib flag under elaboration in the DVM config file

Waveform GUI

To open Vivado waveform viewer use the -gui option. This option opens GUI loading the latest generated waveform dump db by default. To specify a waveform dump db to open use the -dumpfile option.

Coverage report

To generate a coverage report from the latest simulation run use the -genc option. To open the coverage report dashboard use the -cdash option.

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