CX4 Accuracy Improvements - #305
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- Extra cycles tick down at 20MHz effective instead of 80MHz - JP takes 3 20MHz cycles if taken, 1 if not taken - SKIP takes 2 20MHz cycles if taken, 1 if not taken
- Set wait cycles based on current opcode, not next - Fix BUSRD never returning to idle when finished
- For OP_JP and OP_WAI, wait in ST_CPU_1 for their respective conditions instead of taking the full instruction loop every time - Adjust bus read delay from 9 to 10
mrehkopf
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Aug 25, 2026
| if(cpu_wait_subcyc == 2'b11) begin | ||
| cpu_wait_subcyc <= 2'b00; | ||
| cpu_wait <= cpu_wait - 1; | ||
| if(cpu_wait == 8'h01) CPU_STATE <= ST_CPU_0; |
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With cpu_wait == 8'h00 as set by non-taken branches and SPEED set to normal, doesn't this make the CPU wait for 255 cycles before continuing to ST_CPU_0?
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Thanks for the review! The CPU only ever goes to ST_CPU_4 on taken branches, so I believe that case isn't possible unless there's a mistake in my logic. I wasn't able to see any though.
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One other thing I had in mind but didn't implement was using WS1 for the bus read delay. I wasn't sure what the best way of implementing that would be because I don't have a full understanding of how the core reads from the bus and how many cycles that really takes, and how you would take that into account when using WS1, so I opted for adjusting the constant. With the other changes, 16 ran too slow compared to original carts, but 10 has very close results in MMX2/3.
Other than CX4-lag heavy sections and wireframe timing being more accurate to the original carts, one of the more significant improvements with these changes is that the X2 intro demo now syncs, whereas before X would end up dying. Here's a video with some quick comparisons: https://www.youtube.com/watch?v=5g1n6vVjAMc
These changes were only tested on a MK2 since that's the only SD2SNES I own.