Support save states on the DSP, SA-1, GSU, CX4, OBC1 and S-DD1 cores

[ludufre]

Savestates originally only worked with games without a special chip, because the
firmware loads a different FPGA core for those and it had no in-game hook to run
custom code from. The coprocessor cores now carry that machinery, so savestates
also work on:

Chip	Core	Notes
DSP1-4 (uPD7725)	fpga_dsp	ST0010 (uPD96050) is not covered
SA-1	fpga_sa1	Mk.III only (does not fit the Mk.II FPGA)
Super FX / GSU	fpga_gsu
CX4	fpga_cx4
OBC1	fpga_obc1
S-DD1	fpga_sdd1

On the Mk.II the GSU and CX4 cores had no room left on the FPGA for both the
savestate machinery and the six hardware ROM-cheat comparators, so on those two
cores (Mk.II only) ROM cheats are applied by patching the loaded ROM image
instead. They work as before with one difference: the in-game cheat toggle no
longer switches ROM codes on and off, those follow the setting as it was when the
game was loaded. WRAM cheats are unaffected, and the Mk.III is unchanged.