SPC7110: add support (FPGA core + firmware)

[ludufre]

This adds a working SPC7110 core to Mk.II and Mk.III.

The chip logic is derived from the ares emulator's C++ implementation (ISC license). The decompressor, data port, ALU and bank mapper are a Verilog re-implementation of sfc/coprocessor/spc7110/, and the ISC notice is carried verbatim in those files. ISC is permissive, so the combined work stays GPL-2.0-only like the rest of the repository. The RTC-4513 interface is the one part not taken from ares; it was written from public docs (nocash fullsnes, nesdev) and is cited as such. No other SPC7110 implementation was referenced.

The core is based on the S-DD1 core, which is the closest relative (a decompressor that reads the ROM behind the SNES's back, same PSRAM slot-stealing discipline). The frame (main.v, arbiter, support modules) comes from it, most files byte-identical. The firmware hands the core the data-ROM window over PSRAM via two new SPI commands ($d7/$d8, unused by every existing core).

Mk.III gets a virtual RTC battery, Mk.II is bypassed. The RTC-4513 can be stopped by the game, and a stopped clock must survive a power cycle, which is what the cartridge's factory check program tests. On Mk.III the firmware keeps the clock state in a 24-byte .rtc sidecar next to the .srm, same idea as the Super Game Boy's .gtc. On Mk.II there is no room for that (the core already sits at 92% of the Spartan-3), so the clock runs from console wall time and the firmware seeds the retail signature into SRAM to skip the factory check.

[Ramsis-SNES]

Wow! Exciting! 👍 🥇