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[SPI_Master.v] only start when ready #7

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[SPI_Master.v] only start when ready #7

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2 changes: 1 addition & 1 deletion Verilog/source/SPI_Master.v
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ module SPI_Master
r_Leading_Edge <= 1'b0;
r_Trailing_Edge <= 1'b0;

if (i_TX_DV)
if (i_TX_DV && o_TX_Ready)
begin
o_TX_Ready <= 1'b0;
r_SPI_Clk_Edges <= 16; // Total # edges in one byte ALWAYS 16
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