fix(rocm): avoid pointer-select crash in DSV4 sparse attention - #33
Draft
nekomario28 wants to merge 1 commit into
Draft
fix(rocm): avoid pointer-select crash in DSV4 sparse attention#33nekomario28 wants to merge 1 commit into
nekomario28 wants to merge 1 commit into
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Review/delivery carrier
This is an upstream-ready review carrier, not a merge target for this fork's diverged
main. The base branchreview/upstream-main-f7c31eis an immutable snapshot of currentFlashML-org/FreeTokenmain atf7c31e92dbf296de3a5bb1b9c5fcb58f988e3a07so the diff remains exactly one upstream-reviewable file.Summary
Avoid an AMD Triton compiler assertion in both DSV4 sparse-attention paths by preserving the existing single-load pointer-select path on CUDA and using separately masked window/compressed pool loads only on ROCm.
Changed file only:
python/freetoken/kernel/triton/dsv4/sparse_attn.pyHead commit:
51a2d2ad7d22b2ce05eee6fa80f11cf52fbee6c9Root cause
On RX 7800 XT (
gfx1101) with PyTorch2.11.0+rocm7.2, HIP7.2.26015, Triton3.6.0, both decode and prefill reproduced the same AMD compiler assertion inTritonAMDGPUCanonicalizePointers:ConvertArithSelectOp: expected can narrow to be the same for both fatPtrT and fatPtrFThe failing IR came from the pointer-valued
tl.where(is_win, win_ptr, cmp_ptr). This matches the failure class tracked intriton-lang/triton#9859.Fix shape
SEPARATE_POOL_LOADS: tl.constexpris enabled only whentorch.version.hip is not None.tl.load, preserving the existing shared-memory design constraint for consumer Blackwell.Physical RED → GREEN evidence
Baseline RED:
32932005040, job98065895708gfx1101m=1, split-k: RED_REPRODUCEDm=2: RED_REPRODUCEDTritonAMDGPUCanonicalizePointersHypothesis discriminator:
32932483894, job98067252224Exact clean commit validation:
32933110257, job9806902616051a2d2ad7d22b2ce05eee6fa80f11cf52fbee6c9f7c31e92dbf296de3a5bb1b9c5fcb58f988e3a077dcefe54183b12864a64d4cde82f2bcc63fa87fba6efd0490949a9ca8bac8c83d8bca9caa59596189676bd67809b9c442964fd37splits=3splits=0Claim boundary
This proves the exercised DSV4 decode/prefill paths on RX 7800 XT / gfx1101 / ROCm 7.2 / Triton 3.6.0. It does not claim performance parity, full DSV4 model serving, all ROCm/Triton versions, or physical NVIDIA regression.
A direct upstream PR was attempted but the connected GitHub integration returned
403 Resource not accessible by integration; this carrier preserves the exact upstream-ready diff and evidence until an authorized GitHub/CLI path can deliver it.