Verilog_Design

System Level Design of a wide array of synchronous and asynchronous circuits using Verilog.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
Factorial-Calculator		Factorial-Calculator
Hierarchical Design of a CLA Adder		Hierarchical Design of a CLA Adder
Sequential Building Blocks		Sequential Building Blocks
Single-Cycle_Mips_Processor		Single-Cycle_Mips_Processor
Storage Building Blocks		Storage Building Blocks
System Level Design - Divider		System Level Design - Divider
System Level Design		System Level Design
UPDATED CALC		UPDATED CALC
and_or		and_or
voting_machine		voting_machine
README.md		README.md

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