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Fix cqhci halt check at the release tag of lf-6.6.36-2.1.0#44

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phytec-india:fix-cqhci-halt-check
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Fix cqhci halt check at the release tag of lf-6.6.36-2.1.0#44
phyin-dj09 wants to merge 10000 commits into
nxp-imx:lf-6.12.yfrom
phytec-india:fix-cqhci-halt-check

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Summary

Fix incorrect CQHCI_HALT bit check in drivers/mmc/host/cqhci-core.c.

Problem

The linux-imx 6.6.36 branch checks CQHCI_HALT using logical AND:

if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)

Since CQHCI_CTL is a bitfield register, the HALT bit must be checked
using bitwise AND.

Impact

The current implementation may incorrectly interpret the CQE state
whenever CQHCI_CTL contains any non-zero value.

On a PHYTEC phyCORE-i.MX8MM based custom board booting from external
eMMC, this resulted in intermittent boot hangs after repeated hard
reboots.

Fix

Replace logical AND with bitwise AND.

Validation

  • Board: PHYTEC phyCORE-i.MX8MM based custom board
  • Boot media: external eMMC
  • Kernel: linux-imx 6.6.36
  • CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
  • 100 consecutive hard reboot cycles passed

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