feat: synchronize OpenROAD timing and parasitics

.gitignore

@@ -32,6 +32,7 @@
 *.app
 
 build
+build-*/
 .vscode
 .cache
 .codex

.gitmodules

@@ -1,4 +1,4 @@
 [submodule "thirdparty/OpenROAD"]
 	path = thirdparty/OpenROAD
 	url = https://github.com/zhaoxueyan1/OpenROAD.git
-	branch = ecc-sizer
+	branch = merge-upstream-master

README.md

@@ -99,6 +99,35 @@ These files may contain benchmark-specific paths or contest-flow assumptions.
 Before running on a new design, update the Liberty, LEF, Verilog, SDC, DEF,
 SPEF, output, and top-module settings for your local benchmark environment.
 
+Equivalent-cell candidates are grouped through OpenROAD/OpenSTA equivalence
+classes. Candidate order can be selected in the command file or environment
+file:
+
+```text
+-equiv_cell_sort drive_resistance
+-equiv_cell_sort leakage
+```
+
+The default is `drive_resistance`, which follows the OpenSTA equivalent-cell
+order. The `leakage` mode sorts candidates in each equivalence class by leakage
+power first.
+
+Parasitic estimation defaults to placement RC. Set the following command-file
+option to run global routing and estimate RC from the routed topology after
+detailed placement:
+
+```text
+-use_gr_rc 1
+```
+
+The accepted values are `0` and `1`; the default is `0`.
+
+For single-VT libraries, `leakage` sorting is usually a good starting point
+because the timing spread within an equivalence class is relatively limited and
+lower-leakage candidates can improve the power/timing tradeoff. For multi-VT
+libraries, `drive_resistance` sorting is recommended because candidate ordering
+should preserve timing convergence before favoring lower-leakage, slower cells.
+
 ## Submodule Notes
 
 The top-level repository tracks OpenROAD as a submodule. OpenROAD then tracks

src/analyze_timing.cpp

@@ -458,13 +458,21 @@ void designTiming::getTranVio(double &tot, double &max, int &num) {
         _tclInputString = "OSGetTranVio ";
         double begin = cpuTime();
         auto design = _sizer->_ckt->_ord_design;
+        sta::dbNetwork* network =
+            _sizer->_ckt->_ord_timing->getSta()->getDbNetwork();
         ofstream ofs("opensta_tran_vio.txt");
         for(auto inst : design->getBlock()->getInsts()) {
             for(auto pin_ : inst->getITerms()) {
                 if(pin_->getNet() && pin_->getNet()->getSigType() != "POWER" &&
                    pin_->getNet()->getSigType() != "GROUND" &&
                    pin_->getNet()->getSigType() != "CLOCK") {
                     auto m_term = pin_->getMTerm();
+                    sta::Port* port = network->dbToSta(m_term);
+                    sta::LibertyPort* lib_port =
+                        port ? network->libertyPort(port) : nullptr;
+                    if(lib_port == nullptr) {
+                        continue;
+                    }
                     double r_slew = _sizer->_ckt->_ord_timing->getPinSlew(
                         pin_, ord::Timing::Rise);
                     double f_slew = _sizer->_ckt->_ord_timing->getPinSlew(
@@ -517,18 +525,25 @@ void designTiming::getCapVio(double &tot, double &max, int &num) {
         auto design = _sizer->_ckt->_ord_design;
         ofstream ofs("opensta_cap_vio.txt");
         auto corner = _sizer->_ckt->_ord_timing->getCorners()[0];
+        sta::dbSta *sta = _sizer->_ckt->_ord_timing->getSta();
+        sta::dbNetwork* network = sta->getDbNetwork();
         for(auto inst : design->getBlock()->getInsts()) {
             for(auto pin_ : inst->getITerms()) {
                 if(pin_->getNet() && pin_->getNet()->getSigType() != "POWER" &&
                    pin_->getNet()->getSigType() != "GROUND" &&
                    pin_->getNet()->getSigType() != "CLOCK" &&
                    pin_->isOutputSignal()) {
                     auto m_term = pin_->getMTerm();
+                    sta::Port* port = network->dbToSta(m_term);
+                    sta::LibertyPort* lib_port =
+                        port ? network->libertyPort(port) : nullptr;
+                    if(lib_port == nullptr) {
+                        continue;
+                    }
                     float pin_cap;
                     float wire_cap;
-                    sta::dbSta *sta = _sizer->_ckt->_ord_timing->getSta();
                     sta::Net *sta_net =
-                        sta->getDbNetwork()->dbToSta(pin_->getNet());
+                        network->dbToSta(pin_->getNet());
                     _sizer->_sta->connectedCap(
                         sta_net, corner, sta::MinMax::max(), pin_cap, wire_cap);
                     wire_cap /= _sizer->cap_unit;

src/calc.cpp

@@ -644,12 +644,19 @@ void Sizer::UpdateCapsFromCells() {
                         string pin_name = getFullPinName(pins[view][input_j]);
                         auto pin_ = _ckt->_ord_design->getBlock()->findITerm2(
                             pin_name.c_str());
+                        if(pin_ == nullptr) {
+                            continue;
+                        }
                         sta::dbSta* sta = _ckt->_ord_timing->getSta();
                         sta::dbNetwork* network = sta->getDbNetwork();
                         sta::Port* port = network->dbToSta(pin_->getMTerm());
-                        sta::LibertyPort* lib_port = network->libertyPort(port);
+                        sta::LibertyPort* lib_port =
+                            port ? network->libertyPort(port) : nullptr;
                         sta::LibertyLibrary* lib =
                             network->defaultLibertyLibrary();
+                        if(lib_port == nullptr) {
+                            continue;
+                        }
                         pins[view][input_j].cap =
                             lib_port->capacitance() / cap_unit;
                         lib_cell_info->pins[pins[view][input_j].lib_pin]
@@ -689,6 +696,17 @@ double Sizer::CalcCapViolation(unsigned view) {
                         getFullPinName(pins[view][cells[i].outpins[k]]);
                     auto pin_ = _ckt->_ord_design->getBlock()->findITerm2(
                         pin_name.c_str());
+                    if(pin_ == nullptr) {
+                        continue;
+                    }
+                    sta::dbSta* sta = _ckt->_ord_timing->getSta();
+                    sta::dbNetwork* network = sta->getDbNetwork();
+                    sta::Port* port = network->dbToSta(pin_->getMTerm());
+                    sta::LibertyPort* lib_port =
+                        port ? network->libertyPort(port) : nullptr;
+                    if(lib_port == nullptr) {
+                        continue;
+                    }
                     double cap_limit =
                         _ckt->_ord_timing->getMaxCapLimit(pin_->getMTerm()) /
                         cap_unit;
@@ -748,6 +766,13 @@ double Sizer::CalcCapViolation(unsigned view) {
                 }
                 float pin_cap2;
                 float wire_cap2;
+                sta::dbNetwork* network = sta->getDbNetwork();
+                sta::Port* port = network->dbToSta(pin_->getMTerm());
+                sta::LibertyPort* lib_port =
+                    port ? network->libertyPort(port) : nullptr;
+                if(lib_port == nullptr) {
+                    continue;
+                }
                 sta->connectedCap(sta_net, _corner, sta::MinMax::max(),
                                   pin_cap2, wire_cap2);
                 wire_cap2 /= cap_unit;