feat(iSTA): support generated clocks and common SDC constraints

[yipeix]

SDCs using generated clocks, clock groups and common collection/transition commands could fail to load or continue with incomplete timing constraints. This change adds their iSTA implementations and stops initialization when an SDC contains invalid or unsupported constraints.

• Add ideal generated clocks and waveform-aware setup/hold edge pairing. Report launch and capture clocks separately.
• Add clock-group and from/to false-path filtering while preserving valid alternative paths through reconvergence.
• Add pin/port/clock queries, all_inputs/all_outputs, current_design and remove_from_collection, including wildcard/regexp handling and literal bus names.
• Apply set_clock_transition to ideal clock slew used in clock-to-Q and setup/hold lookup; fix set_clock_uncertainty for collections of clocks. Initialize Tcl's standard library so expr min(...) works and validate scalar numeric arguments.
• Import Liberty fanout attributes, evaluate design/port/pin limits and emit max_fanout text/JSON reports plus QoR violation counts.

Validation:

• Release ecc_bin build and three local regression programs covering SDC timing semantics, Liberty fanout parsing and arc delay selection.
• NPC TT run with the supplied 100 MHz SDC, ideal clock and no SPEF; timing and fanout reports generated successfully.
• git diff --check.

The regression harness changes under src/operation/iSTA/test remain local and are excluded from this PR.

Scope: generated clocks with propagated internal sinks and overlapping internal clock modes are explicitly rejected. Through-point/edge-specific false-path selectors, full typed collections and constraint-removal commands remain unsupported. The implementation was written independently against iSTA data structures; no OpenSTA code was copied.