fix(iSTA): restore SRAM bus timing and show path fanout - #231
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ZhishengZeng
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Sep 14, 2026
ZhishengZeng
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September 15, 2026 01:49
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Liberty bus members were omitted from the iSTA port model, and timing groups under bus pins were attached to the bus or last pin instead of each bit. This dropped SRAM setup/hold and clock-to-Q arcs and produced optimistic timing results.
This change expands ascending and descending pin ranges, applies inherited bus attributes before per-bit overrides, parses each bit's tables independently, restores the enclosing parser context, and resolves bus indices by their actual bit names. iSTA now imports bus-member ports and their internal-power data alongside scalar ports. Both Liberty visitor entry points use the same pin implementation.
Detailed timing RPTs now show physical load-pin counts in a
Fanoutcolumn afterPoint, withIncrandPathon the same aligned row. Driver rows count unique connected load pins, including output ports; non-driver and clock/constraint summary rows leave the count blank. Weighted Liberty fanout checks keep their existing meaning.Validation: