fix(iSTA): improve RC timing accuracy and add optional minimum slew policy - #236
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September 16, 2026 04:00
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Input-port RC delays and SDF data-pin slew selection produced significant local timing differences. This change evaluates the reduced RC network's step/ramp waveform for input ports and uses data slew, with a physical clock-waveform fallback, for SDF data checks. Explicit zero data slew remains valid.
It also adds
init_sta -min_slew_degradation 0|1consistently to Tcl, C++ and Python configuration. The default1retains calculated receiver slew. Experimental mode0uses moment-reduced pi resistance to select a driver-slew approximation for minimum analysis, only when the receiver has matching slew thresholds and derate. Mixed conventions retain their physical waveform. Wire-delay threshold corrections, maximum analysis, resistance loops and DMP fallback keep their existing behavior. The approximation remains opt-in and does not claim full PrimeTime alignment.Merged the latest
main(c63838af1, including the Abseil-to-STL migration) intosta_timing_main. OpenSTA was consulted for behavior; the implementation is original.Validation:
ecc_binbuild and all 9 local CTests pass on the integrated code, covering RC waveforms, configuration validation, mixed receiver conventions, caching, SDF checks, Liberty buses and SDC semantics.Example6 SDF evidence from the validated implementation, using the same PT reference and pairing by instance, pins, transition, condition and min/max (absolute differences, ps):
The experimental policy still worsens some values relative to the default. Remaining driver-model differences and SDF RETAIN, disabled-arc and conditional-check coverage are not hidden or considered resolved.