[Bug] Harden flow passes severe slew and timing violations without physical timing repair

[WilliamHHL]

Summary

The current hardening flow can complete placement/routing while leaving severe transition and setup violations, yet its QoR summary reports CAP=0, TRAN=0, TDRC=0 and stage quality pass. On a 100 MHz macro SoC, independent OpenROAD/OpenSTA analysis confirms a real Fmax of only about 44-46 MHz.

The low Fmax is not an iSTA interpolation bug: OpenSTA reproduces the same multi-nanosecond cell delays caused by extreme slew on minimum-drive cells. The flow has fanout buffering and CTS, but no effective post-placement timing repair/resizing stage.

Versions

• ECC: f783db8d8c4d22559993d27ddeac314fa35a58ca
• ecc-tools: 33617742b6dbaaa4dd6711def4bf81d4920d3bfc
• DreamPlace: dcc67cd85ca02fab0337cbcf08b59bcbccc0be01
• PDK: ICS55
• Target: 100 MHz, macro SoC, physical utilization about 54%

Current ECC/iSTA result

setup WNS = -11.923 ns
setup TNS = -72,288.3 ns
violating paths = 11,988
estimated Fmax = 46 MHz
CAP=0 FANOUT=0 TRAN=0 TDRC=0

The worst path includes:

AOI211X0P5H7R cell delay = 6.451794 ns

Its output net has one sink and about 0.116 pF extracted capacitance. The large delay is driven by very poor slew, not a single ultra-high-fanout data net.

Independent OpenROAD/OpenSTA control

Using the same routed DEF, RC-worst SPEF, Liberty files, and 10 ns SDC:

setup WNS = -12.558320 ns
setup TNS = -84,091.367188 ns
hold WNS  = -0.035856 ns

For the same worst-path cell:

capacitance = 0.117125 pF
output slew = 10.877978 ns
cell delay  = 6.446505 ns
max-slew limit near the path = 0.795659 ns

Thus OpenSTA and iSTA agree on the pathological data delay. The ECC QoR fields showing zero transition violations do not represent a clean design.

Flow observations

• DreamPlace is forced to timing_opt_flag=0 and with_sta=False in chipcompiler/tools/ecc_dreamplace/module.py.
• The flow inserts fanout buffers, but it does not run an equivalent of timing-driven sizing/buffering such as OpenROAD repair_design/repair_timing after placement and CTS.
• Post-CTS SDC generated by create_default_sdc() contains only create_clock; it does not request propagated clocks.
• Route/STA checklists can pass without populated transition/capacitance checks or without timing closure.

Expected behavior

For a hardening/signoff preset:

1. Run timing-driven cell sizing/buffering and hold repair after physical parasitics are available.
2. Populate max transition, capacitance, fanout, setup, and hold checks from real STA data.
3. Fail hardening quality when those checks violate configured limits.
4. Use propagated clocks after CTS (subject to the separate current iSTA propagation defect).
5. Preserve both configured target frequency and achieved signoff frequency in the QoR output.

This is related to CTS configuration issue #221, but the current run no longer has an unbuffered 13k-sink raw clock net. The remaining dominant setup failure is data-path slew and missing timing repair, so CTS configuration alone does not resolve it.

[WilliamHHL]

Density-0.65 routed follow-up: placement round trip and electrical violations

A second current-main macro-SoC run at 65% requested core utilization strengthens this issue. OpenROAD/OpenSTA 26Q3-1305-gf552262465, using the same routed DEF, SDC, Liberty files, and SPEFs as ECC/iSTA, closely reproduces setup timing:

Corner	iSTA Fmax estimate	OpenSTA Fmax estimate
SS/125C/RCworst	8.695 MHz	8.965 MHz
TT/25C/TYPICAL	27.251 MHz	28.951 MHz
FF/-40C/RCbest	57.763 MHz	59.839 MHz

The same CPU register-to-register path is worst in both tools. At TT, OpenSTA reports these electrical violations:

max-slew violations:       27,100
max-capacitance violations: 2,276
max-fanout violations:          0

The worst path demonstrates why max-fanout repair is insufficient:

_081689_ at (402.2, 135.0) -> _081690_ at (399.8, 287.6): ~155.0 um Manhattan, fanout 1
_081690_ at (399.8, 287.6) -> _081691_ at (397.8, 130.8): ~158.8 um Manhattan, fanout 1

The two adjacent combinational stages travel about 155 um upward and immediately 159 um back. OpenSTA reports:

_081689_/Y: cap 0.202 pF, slew 9.461 ns, cell delay 5.457 ns
_081690_/Y: cap 0.173 pF, slew 17.398 ns, cell delay 13.501 ns
max-slew limit near the path: 0.796 ns

This is direct evidence that the hardening flow lacks effective timing-driven placement plus max-slew/max-cap buffering and resizing. Density may aggravate placement pressure, but the demonstrated failure cannot be corrected by fanout repair or CTS alone. The flow should gate completion on real transition/capacitance checks and run electrical/timing repair after placement and routing.