Title: [Bug] DELAY-family ABC strategies (retime/mfs/buffer-upsize fine-tune)
make block-scale netlists routing-hostile: 4.5-5.5x more DRT violations than a
plain mapping script, with LOWER Fmax
Self checks
ECC version
ecc 1f910c3 (frozen M1); strategy code identical on current main
(yosys_synthesis.tcl DELAY family, indexes 0-13).
Affected area
Synthesis (yosys ABC strategy: tools/yosys/scripts/yosys_synthesis.tcl)
Environment
- OS: Ubuntu 26.04 LTS, x86_64
- PDK: ICS55 (icsprout55-pdk), dual-VT std cells
- Design: ~94k-cell MCU SoC with two SRAM macros, util 0.65, MET1-5, 10ns clock
Steps to reproduce
- Synthesize a block-scale SoC with the DELAY family (e.g. "DELAY 4").
- Re-synthesize the SAME RTL with a plain script
(+fx;strash;refactor;resyn2;scleanup;map;&get,-n;&st;&dch;&nf;&put;
print_stats -m — via the ABC_RAW_SCRIPT env we added locally).
- Route both netlists with the same backend and compare DRT.
Expected behavior
Timing-driven strategies (retime, mfs, choice, map_tight, buffer/upsize/dnsize
fine-tune) should improve or at least not harm routability for their timing
cost — and should not LOSE Fmax to a plain mapping.
Actual behavior
OpenROAD 26Q3-1305, identical flow (same frozen design, MET1-5, util 0.65):
| netlist |
DRT1 |
9-iter floor |
TT ideal Fmax |
| DELAY0-style |
253,536 |
106,188 |
~273.9 MHz |
| plain "safe" script |
46,248 |
12,294 |
~297.7 MHz |
- 5.5x DRT1, 8.6x floor improvement, +24 MHz Fmax — the aggressive script
bought nothing and lost routability.
- keep_hierarchy ON vs OFF: DRT identical — the script is the lever, not
hierarchy.
ECC flow (our replication, same PDK/design family):
| netlist |
GRT overflow |
DRT1 |
| DELAY-4 (default) |
54,049-56,611 |
529,705-572,013 |
| safe script + X0P5 dont_use |
5,559-6,038 |
100,150-106,951 |
- 4.5-5x on ECC's own router too — the effect is tool-independent.
Interpretation
The DELAY family's transforms (retime across flops, mfs deep AOI/OAI
factorization, if -K 6 choice exploration, and the buffer/upsize/dnsize
fine-tune) create deep AOI/OAI/MUX clusters and inflated cell counts. Both
correlate with local detail-route congestion (hotspots measured in AOI/OAI
pockets). On this design the aggressive scripts provided no timing benefit
(plain mapping was FASTER) while multiplying DRT violations.
Suggested fix
- Provide a routability-friendly default strategy (the plain script above or
a BALANCE-family equivalent without retime/fine-tune) for block-scale
designs, and/or make the strategy family selectable per design scale.
- Audit why retime/mfs/upsize-buffer fine-tune raises DRT ~5x on block
designs (structural vs cell-count mechanism) — a calibration pass against
a routability metric would prevent the timing knobs from outrunning
routability.
- Minor: the bundled yosys/abc does not know the 'resyn2' alias
("unknown command 'resyn2'") — we expanded it to its standard definition
locally.
Related
- ecc-tools#198 (router regional-repair gate), ecc-dreamplace#35 (EGR
density inflation), ecc-dreamplace#31, ecc#155 — same design investigation.
- ecc#257 (local congestion support request) — the routing-side tool gap
remains after this synthesis fix.
Title: [Bug] DELAY-family ABC strategies (retime/mfs/buffer-upsize fine-tune)
make block-scale netlists routing-hostile: 4.5-5.5x more DRT violations than a
plain mapping script, with LOWER Fmax
Self checks
ECC version
ecc 1f910c3 (frozen M1); strategy code identical on current main
(yosys_synthesis.tcl DELAY family, indexes 0-13).
Affected area
Synthesis (yosys ABC strategy: tools/yosys/scripts/yosys_synthesis.tcl)
Environment
Steps to reproduce
(+fx;strash;refactor;resyn2;scleanup;map;&get,-n;&st;&dch;&nf;&put;
print_stats -m — via the ABC_RAW_SCRIPT env we added locally).
Expected behavior
Timing-driven strategies (retime, mfs, choice, map_tight, buffer/upsize/dnsize
fine-tune) should improve or at least not harm routability for their timing
cost — and should not LOSE Fmax to a plain mapping.
Actual behavior
OpenROAD 26Q3-1305, identical flow (same frozen design, MET1-5, util 0.65):
bought nothing and lost routability.
hierarchy.
ECC flow (our replication, same PDK/design family):
Interpretation
The DELAY family's transforms (retime across flops, mfs deep AOI/OAI
factorization, if -K 6 choice exploration, and the buffer/upsize/dnsize
fine-tune) create deep AOI/OAI/MUX clusters and inflated cell counts. Both
correlate with local detail-route congestion (hotspots measured in AOI/OAI
pockets). On this design the aggressive scripts provided no timing benefit
(plain mapping was FASTER) while multiplying DRT violations.
Suggested fix
a BALANCE-family equivalent without retime/fine-tune) for block-scale
designs, and/or make the strategy family selectable per design scale.
designs (structural vs cell-count mechanism) — a calibration pass against
a routability metric would prevent the timing knobs from outrunning
routability.
("unknown command 'resyn2'") — we expanded it to its standard definition
locally.
Related
density inflation), ecc-dreamplace#31, ecc#155 — same design investigation.
remains after this synthesis fix.