feat(flow): add DreamPlace macro placement step

chipcompiler/cli/core/output.py

@@ -13,7 +13,9 @@ def disclosure_cmd(command: str, project: str | None = None, workspace: str | No
 def normalize_step_name(internal: str) -> str:
     mapping = {
         "Synthesis": "synthesis",
-        "Floorplan": "floorplan",
+        "preFloorplan": "pre_floorplan",
+        "macroPlacement": "macro_placement",
+        "postFloorplan": "post_floorplan",
         "place": "placement",
         "CTS": "cts",
         "legalization": "legalization",

chipcompiler/cli/project/design_inputs.py

@@ -23,6 +23,8 @@ class ResolvedDesignInputs:
 
 _PHYSICAL_STEPS = frozenset(
     {
+        "macroPlacement",
+        "postFloorplan",
         "place",
         "CTS",
         "legalization",
@@ -46,7 +48,7 @@ def required_inputs_for_step(step: str) -> tuple[str, ...]:
         return ("rtl",)
     if canonical in {"lec", "postRouteLec"}:
         return ("netlist", "golden_netlist")
-    if canonical == "Floorplan":
+    if canonical == "preFloorplan":
         return ("netlist",)
     if canonical == "sta":
         return ("def", "netlist", "spef")

chipcompiler/cli/project/manifest.py

@@ -26,7 +26,9 @@
 MANIFEST_FLOW_STEPS = (
     "Synth",
     "LEC",
-    "Floor",
+    "PreFloorplan",
+    "MacroPlacement",
+    "PostFloorplan",
     "Place",
     "CTS",
     "Legal",
@@ -54,7 +56,9 @@
 _CANONICAL_TO_MANIFEST_STEP = {
     "Synthesis": "Synth",
     "lec": "LEC",
-    "Floorplan": "Floor",
+    "preFloorplan": "PreFloorplan",
+    "macroPlacement": "MacroPlacement",
+    "postFloorplan": "PostFloorplan",
     "place": "Place",
     "CTS": "CTS",
     "legalization": "Legal",

chipcompiler/cli/project/migrate_plan.py

@@ -31,7 +31,9 @@
 # Canonical step name -> GUI display name (manifest vocabulary).
 CANONICAL_TO_DISPLAY = {
     "Synthesis": "Synth",
-    "Floorplan": "Floor",
+    "preFloorplan": "PreFloorplan",
+    "macroPlacement": "MacroPlacement",
+    "postFloorplan": "PostFloorplan",
     "fixFanout": "Fanout",
     "place": "Place",
     "CTS": "CTS",

chipcompiler/cli/project/workspace_params.py

@@ -15,7 +15,7 @@
 
 _APPLIES_TO_STEP = {
     "synthesis": "Synthesis",
-    "floorplan": "Floorplan",
+    "floorplan": "preFloorplan",
     "placement": "place",
     "cts": "CTS",
     "routing": "route",

chipcompiler/data/step.py

@@ -11,7 +11,10 @@ class StepEnum(Enum):
     RTL2GDS = "RTL2GDS"
     INIT = "Init"
     SYNTHESIS = "Synthesis"
-    FLOORPLAN = "Floorplan"
+    FLOORPLAN = "Floorplan"  # shared floorplan configuration key, not a flow step
+    PRE_FLOORPLAN = "preFloorplan"
+    MACRO_PLACEMENT = "macroPlacement"
+    POST_FLOORPLAN = "postFloorplan"
     PLACEMENT = "place"
     CTS = "CTS"
     TIMING_OPT = "Timing optimization"

chipcompiler/data/step_dirs.py

@@ -14,7 +14,9 @@
 STEP_DIRECTORIES = {
     StepEnum.SYNTHESIS.value: "Synthesis_yosys",
     StepEnum.LEC.value: "lec_yosys_lec",
-    StepEnum.FLOORPLAN.value: "Floorplan_ecc",
+    StepEnum.PRE_FLOORPLAN.value: "preFloorplan_ecc",
+    StepEnum.MACRO_PLACEMENT.value: "macroPlacement_dreamplace",
+    StepEnum.POST_FLOORPLAN.value: "postFloorplan_ecc",
     StepEnum.PLACEMENT.value: "place_dreamplace",
     StepEnum.CTS.value: "CTS_ecc",
     StepEnum.LEGALIZATION.value: "legalization_dreamplace",

chipcompiler/data/workspace/__init__.py

@@ -161,6 +161,7 @@ def log_workspace_step(step: WorkspaceStep, logger: Logger):
     StepEnum.CTS.value: "cts_ecc.json",
     StepEnum.DRC.value: "drc_ecc.json",
     StepEnum.FLOORPLAN.value: "floorplan_ecc.json",
+    "macro_location": "macro_localtion.tcl",
     StepEnum.ROUTING.value: "route_ecc.json",
     StepEnum.FILLER.value: "filler_ecc.json",
     StepEnum.RCX.value: "rcx_ecc.json",
@@ -183,7 +184,9 @@ def log_workspace_step(step: WorkspaceStep, logger: Logger):
 _STEP_BY_VALUE: Final[dict[str, StepEnum]] = {step.value: step for step in StepEnum}
 
 _STEP_CONFIG_KEYS: Final[dict[tuple[StepEnum, str], tuple[str, ...]]] = {
-    (StepEnum.FLOORPLAN, "ecc"): ("db", StepEnum.FLOORPLAN.value),
+    (StepEnum.PRE_FLOORPLAN, "ecc"): ("db", StepEnum.FLOORPLAN.value),
+    (StepEnum.MACRO_PLACEMENT, "dreamplace"): ("dreamplace", "macro_location"),
+    (StepEnum.POST_FLOORPLAN, "ecc"): ("db", StepEnum.FLOORPLAN.value, "macro_location"),
     (StepEnum.PLACEMENT, "ecc"): ("db",),
     (StepEnum.CTS, "ecc"): ("db", StepEnum.CTS.value),
     (StepEnum.ROUTING, "ecc"): ("db", StepEnum.ROUTING.value),
@@ -550,7 +553,7 @@ def _refresh_floorplan_config(workspace: Workspace, step: WorkspaceStep | None =
     default_ifp = default_floorplan.get("ifp", {})
     ifp.setdefault("thread_number", default_ifp.get("thread_number", 16))
     if step is not None:
-        workdir = step.data.workdir_for(StepEnum.FLOORPLAN.value)
+        workdir = step.data.workdir_for(step.name)
         if workdir:
             ifp["temp_directory_path"] = path_text(workdir)
 
@@ -943,7 +946,7 @@ def update_step_config(workspace: Workspace, step: WorkspaceStep) -> None:
     db["OUTPUT"]["output_dir_path"] = path_text(step.output.dir)
     json_write(workspace.config["db"], db)
 
-    if step.name == StepEnum.FLOORPLAN.value:
+    if step.name in {StepEnum.PRE_FLOORPLAN.value, StepEnum.POST_FLOORPLAN.value}:
         _refresh_floorplan_config(workspace, step=step)
 
     if step.name == StepEnum.ROUTING.value and isinstance(step.data, EccData):

chipcompiler/docs/ecc-config-ref.cn.md

@@ -66,7 +66,9 @@ graph LR
 |---|---|---|---|
 | synthesis | — | `global_var.tcl`（Tcl） | Yosys 用 Tcl 变量驱动，不走 JSON |
 | lec | — | 无（Tcl） | 综合级 Yosys LEC；比较综合网表与 golden 网表；未证明时步骤失败并终止后续流程 |
-| floorplan | ✓ | `floorplan_ecc.json` | |
+| preFloorplan | ✓ | `floorplan_ecc.json` | 自动宏布局 |
+| macroPlacement | — | `dreamplace_ecc.json` + `macro_localtion.tcl` | 写入 Tcl 宏摆放交接文件 |
+| postFloorplan | ✓ | `floorplan_ecc.json` + `macro_localtion.tcl` | 读取 Tcl 宏摆放交接文件 |
 | placement | — | `dreamplace_ecc.json` | 与 legalization 共用一个文件 |
 | cts | ✓ | `cts_ecc.json` | |
 | legalization | — | `dreamplace_ecc.json` | 每步重写 `def_input`/`result_dir` 等 |
@@ -228,13 +230,13 @@ tech = "prtech/techLEF/N551P6M_ecos.lef"
 
 ## 4. floorplan（ecc-tools）
 
-配置 `floorplan_ecc.json`，按功能分 6 组。步骤内部子阶段：load data → init floorplan → create tracks → place io pins → tap cell → PDN → set clock net → save data → analysis。
+配置 `floorplan_ecc.json` 由 `preFloorplan` 和 `postFloorplan` 共享。`preFloorplan` 执行 load data → init simple floorplan → save data，并使用自动宏摆放；`macroPlacement` 执行仅宏单元摆放，并通过 `tcl_save` 写入 `config/macro_localtion.tcl` 形成交接检查点；`postFloorplan` 以 `file` 模式读取该文件，再执行 load data → create tracks → place IO pins → tap cells → PDN → set clock net → save data → analysis。
 
 ### ifp（iFP 布图引擎）
 
 | 参数 | 默认 | 含义 |
 |---|---|---|
-| `temp_directory_path` | 每步生成 → `Floorplan_ecc/data/fp` | iFP 中间数据目录 |
+| `temp_directory_path` | 每步生成 → `preFloorplan_ecc/data/fp` 或 `postFloorplan_ecc/data/fp` | iFP 中间数据目录 |
 | `thread_number` | 16 | 并行线程数 |
 
 ### macro_placer（宏摆放）
@@ -285,9 +287,9 @@ tech = "prtech/techLEF/N551P6M_ecos.lef"
 | `stripe`（MET4/MET5） | 宽 1.0、间距 16.0、偏移 0.5 | 电源条带：层/宽度/间距（pitch）/偏移（µm） |
 | `connect_layers` | MET1–MET4、MET4–MET5 | 相邻层电源过孔连接对 |
 
-## 5. placement / legalization（DreamPlace）
+## 5. macro placement / placement / legalization（DreamPlace）
 
-两者共用 `config/dreamplace_ecc.json`；每次步骤运行前重写 `def_input`（placement 读 floorplan 输出，legalization 读 CTS 输出）、`verilog_input`、`result_dir`（分别为 `place_dreamplace/data/pl`、`legalization_dreamplace/data/pl`）。参数即上游 DreamPlace 的 JSON 参数集，分组解释如下（默认值 = 模板值；`*` = 用户参数映射点）。
+三步共用 `config/dreamplace_ecc.json`；每次步骤运行前重写 `def_input`、`verilog_input`、`result_dir`。`macroPlacement` 使用 `macroPlacement_dreamplace/data/macro`；placement 读取 post-floorplan 输出并使用 `place_dreamplace/data/pl`；legalization 读取 CTS 输出并使用 `legalization_dreamplace/data/pl`。参数即上游 DreamPlace 的 JSON 参数集，分组解释如下（默认值 = 模板值；`*` = 用户参数映射点）。
 
 ### 输入输出
 
@@ -311,7 +313,7 @@ tech = "prtech/techLEF/N551P6M_ecos.lef"
 | `enable_fillers` | 1 | 布局阶段允许虚拟 filler 占位（密度计算） |
 | `routability_opt_flag` | 1 `*place.routability_opt` | 绕线拥塞驱动的布局优化 |
 | `timing_opt_flag` / `timing_eval_flag` | 0 | 时序驱动布局（本流程未启用，需 sizer/STA 配合） |
-| `macro_place_flag` | 0 | 宏单元自动摆放（floorplan 已处理） |
+| `macro_place_flag` | 0 | 专用 `macroPlacement` 步骤会启用该开关 |
 | `plot_flag` / `get_congestion_map` / `evaluate_pl` | 0 / 1 / 0 | 出图 / 拥塞图导出 / 布局评估 |
 | `dump_global_place_solution_flag` / `dump_legalize_solution_flag` | 0 | 导出中间解 |
 

chipcompiler/docs/ecc-config-ref.en.md

@@ -66,7 +66,9 @@ Distilled from real `ecc config <step>` output (maps to the source `_STEP_CONFIG
 |---|---|---|---|
 | synthesis | — | `global_var.tcl` (Tcl) | Yosys is driven by Tcl variables, not JSON |
 | lec | — | none (Tcl) | Synthesis-level Yosys LEC; compares the mapped and golden synthesis netlists; an unproven result fails the step and stops the flow |
-| floorplan | ✓ | `floorplan_ecc.json` | |
+| preFloorplan | ✓ | `floorplan_ecc.json` | automatic macro floorplanning |
+| macroPlacement | — | `dreamplace_ecc.json` + `macro_localtion.tcl` | writes the Tcl macro-placement handoff |
+| postFloorplan | ✓ | `floorplan_ecc.json` + `macro_localtion.tcl` | reads the Tcl macro-placement handoff |
 | placement | — | `dreamplace_ecc.json` | shares one file with legalization |
 | cts | ✓ | `cts_ecc.json` | |
 | legalization | — | `dreamplace_ecc.json` | `def_input`/`result_dir` etc. rewritten per step |
@@ -226,13 +228,13 @@ There is also the environment variable `YOSYS_SYNTH_STRATEGY` (e.g. `DELAY 4` /
 
 ## 4. floorplan (ecc-tools)
 
-Configuration file `floorplan_ecc.json`, organized into 6 functional groups. Internal sub-phases of the step: load data → init floorplan → create tracks → place io pins → tap cell → PDN → set clock net → save data → analysis.
+Configuration file `floorplan_ecc.json` is shared by the `preFloorplan` and `postFloorplan` steps. `preFloorplan` runs load data → init simple floorplan → save data with automatic macro placement; `macroPlacement` runs macro-only placement, writes `config/macro_localtion.tcl` through `tcl_save`, and forms the handoff checkpoint; `postFloorplan` consumes that file in `file` mode, then runs load data → create tracks → place IO pins → tap cells → PDN → set clock net → save data → analysis.
 
 ### ifp (the iFP floorplan engine)
 
 | Parameter | Default | Meaning |
 |---|---|---|
-| `temp_directory_path` | generated per step → `Floorplan_ecc/data/fp` | iFP intermediate data directory |
+| `temp_directory_path` | generated per step → `preFloorplan_ecc/data/fp` or `postFloorplan_ecc/data/fp` | iFP intermediate data directory |
 | `thread_number` | 16 | Number of parallel threads |
 
 ### macro_placer (macro placement)
@@ -283,9 +285,9 @@ Configuration file `floorplan_ecc.json`, organized into 6 functional groups. Int
 | `stripe` (MET4/MET5) | width 1.0, pitch 16.0, offset 0.5 | Power stripes: layer/width/pitch (spacing)/offset (µm) |
 | `connect_layers` | MET1–MET4, MET4–MET5 | Adjacent-layer via connection pairs for power |
 
-## 5. placement / legalization (DreamPlace)
+## 5. macro placement / placement / legalization (DreamPlace)
 
-The two steps share `config/dreamplace_ecc.json`; before each step runs, `def_input` (placement reads the floorplan output, legalization reads the CTS output), `verilog_input`, and `result_dir` are rewritten (`place_dreamplace/data/pl` and `legalization_dreamplace/data/pl` respectively). The parameters are exactly the upstream DreamPlace JSON parameter set, explained group by group below (defaults = template values; `*` marks user-parameter mapping points).
+The three steps share `config/dreamplace_ecc.json`; before each step runs, `def_input`, `verilog_input`, and `result_dir` are rewritten. `macroPlacement` uses `macroPlacement_dreamplace/data/macro`, placement reads the post-floorplan output and uses `place_dreamplace/data/pl`, and legalization reads the CTS output and uses `legalization_dreamplace/data/pl`. The parameters are exactly the upstream DreamPlace JSON parameter set, explained group by group below (defaults = template values; `*` marks user-parameter mapping points).
 
 ### Inputs and outputs
 
@@ -309,7 +311,7 @@ The two steps share `config/dreamplace_ecc.json`; before each step runs, `def_in
 | `enable_fillers` | 1 | Allow virtual filler occupancy during placement (for density computation) |
 | `routability_opt_flag` | 1 `*place.routability_opt` | Routing-congestion-driven placement optimization |
 | `timing_opt_flag` / `timing_eval_flag` | 0 | Timing-driven placement (not enabled in this flow; requires sizer/STA support) |
-| `macro_place_flag` | 0 | Automatic macro placement (already handled by floorplan) |
+| `macro_place_flag` | 0 | Enabled for the dedicated `macroPlacement` step |
 | `plot_flag` / `get_congestion_map` / `evaluate_pl` | 0 / 1 / 0 | Plotting / congestion-map export / placement evaluation |
 | `dump_global_place_solution_flag` / `dump_legalize_solution_flag` | 0 | Export intermediate solutions |