feat(#207): flow-level no-clock RTL2GDS (breadth; depends on #206)

[plitenh]

Add a flow.no_clock flag that omits CTS, accepts empty/minimal SDC, and relaxes clock-port/frequency/STA gates so clockless designs can harden without breaking the default clocked path.

What Changed

Scope

Select the areas touched by this PR:

• CLI - command behavior, Typer command surface, output formats, or workspace commands.
• Flow/runtime - workspace lifecycle, EngineFlow, step execution, logs, metrics, or artifacts.
• EDA integration - Yosys, ECC-Tools, DreamPlace, KLayout, PDKs, or native/runtime wrappers.
• Build/package - Nix, PyInstaller, wheels, uv.lock, or release artifacts.
• CI/release - GitHub Actions, version checks, changelog, or release automation.
• Tests/docs only

Runtime And Packaging Impact

• No runtime or packaging impact
• CLI output or machine-readable contract changed
• Workspace layout, flow state, or artifact paths changed
• Native toolchain or wrapper behavior changed
• ecc-tools or ecc-dreamplace dependency changed
• PyInstaller, Nix, or release artifact changed

Notes:

Validation

List the commands you ran. Mark checks that are not applicable as N/A.

• uv run pytest test/
• uv run ruff check chipcompiler test
• uv run ruff format --check chipcompiler test
• PyInstaller smoke: ecc --help, ecc --version, ecc version --json
• Nix smoke: nix run .#cli -- --help
• Manual flow smoke:
• Other:

Skipped checks and reason:

Checklist

• I kept the change scoped to ECC.
• I updated docs or user-facing CLI text where behavior changed.
• I included lockfile or version metadata updates when dependencies changed.
• I documented any submodule updates and why they are needed.
• I did not include local caches, virtual environments, or generated build outputs.
• I explained skipped validation and remaining risk.

[plitenh]

@Emin017

Thanks for the pointer to #206 — we'll redesign #277 under that SDC constraint.

To avoid risky churn while #206 is still settling the template/sdc_load surface, we'll handle #277 as flow breadth only, as follows:

1. Contract for this PR / tests: the final default SDC shape is whatever #206 lands (create_clock on a real port, or VIRTUAL_CLK when clock is empty, plus IO delay / uncertainty / transition / max_fanout / optional set_load). #277 will not ship an empty/placeholder no-clock SDC (no "comment-only" auto SDC without create_clock).

2. Scope split: breadth work (omit CTS, CLI no_clock, reconcile, STA/signoff/QoR gates, tool degrade) may be developed on main or stacked on emin/enhance-sdc. We will not change SDC_HEAD* / sdc_load (or otherwise redesign the SDC shell) inside the breadth PR — that stays #206.

3. Merge order: prefer merge #206 first, then #277 (or retarget #277's base to main once it already contains #206). Until #206 lands, #277 stays Draft with depends on #206.

4. Local workflow: a clean worktree based on synced emin/enhance-sdc or main is fine. If based on main, virtual-clock SDC assertions are marked "enable after #206"; flow/CTS tests can go green first.

[Emin017]

I added skippable step enum in #286, you can refactor the no-clock RTL2GDS flow based on it.