refactor(runtime): consolidate ecc workspace runtime - #284
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Move the public parameter schema and workspace override helpers into the data layer while keeping CLI compatibility facades.
Preserve creator input modes, flow filters, read-only configuration and signoff assessment semantics across CLI and headless APIs.
Reuse the report scoring policy for headless assessments and expose the committed step callback contract.
Keep manifest audit timestamps, tolerate forward-version QoR facts and malformed checklists, and map collector failures to the signoff domain error.
Keep the CLI import paths as module aliases while making Project APIs independent of CLI internals, add read-only workspace loading, and materialize config-target parameters.
Keep configuration updates under an exclusive lock and recover from on-disk backups instead of restoring file bytes from process memory.
Move fail thresholds, weights, and metric selection into qor_scoring. CLI reports and Snapshot assessment call that module; stop documenting a GUI port and a second threshold table.
Studio rejects the whole snapshot QoR section when any analysis metric uses category "power". Restore the canonical power_integrity mapping and remap existing on-disk qor_metrics.json when assembling snapshots.
Studio reads std_cell/macro/io-pad metrics plus database_facts and lvs_connectivity_summary from the snapshot. Emit those from existing feature JSON, and reject STA when pdk.sdc is unset instead of crashing.
Sizer stores Timing Opt as timing_optimization_sizer. Snapshot analysis fell back to Timing optimization_sizer, so Studio showed empty QoR, layout, reports, and subflow for a successful step.
…time-consolidation
Attach the Engineering Snapshot observer to TTY progress runs so each completed step updates home/engineering-snapshot.json, matching execute().
…time-consolidation
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create_workspace only rebinding design.input_filelist in memory meant the filelist input was lost whenever the workspace was reloaded from disk (step subprocesses, later GUI sessions); synthesis then fell back to the single origin verilog and multi-file designs failed hierarchy with "Module <top> not found". Record the frozen filelist path in params.toml (file_list) at creation and restore design.input_filelist from it in the loader, keeping the origin/filelist convention as fallback.
Yell-walkalone
approved these changes
Sep 15, 2026
Emin017
approved these changes
Sep 15, 2026
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uv.lock, or release artifacts.Runtime And Packaging Impact
ecc-toolsorecc-dreamplacedependency changedNotes:
uv.lockand thejsonrpcservercompatibility constraint were updated as part of the dependency metadata changes.Validation
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uv run pytest test/(ranCMAKE_BUILD_PARALLEL_LEVEL=2 uv run --no-sync pytest test/ -q: 2653 passed, 6 skipped, 1 deselected, 4 xfailed)uv run ruff check chipcompiler test(ranuv run --no-sync ruff check chipcompiler test)uv run ruff format --check chipcompiler test(ranuv run --no-sync ruff format --check chipcompiler test)ecc --help,ecc --version,ecc version --jsonnix run .#cli -- --helpbash .github/scripts/check-version.sh;uv lock --check;uv sync --locked --inexact --no-install-package ecc-dreamplace --no-install-package ecc-tools-bin;git diff --check origin/main...HEAD; commit-message checks for all commits and the PR title.Skipped checks and reason:
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