openhwfoundation cva6 · Discussions · GitHub

Discussions

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Agentic CVA6 Platform for Devin/Grok-Build with board dev

etcimon started Jul 22, 2026 in Show and tell

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Branch predictor flush missing signal. Bug?

gm-openchip asked Nov 6, 2025 in Q&A · Answered

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Frontend Instr_realign.sv BUG vlen=64bit

SpoonySneeze asked Jun 30, 2026 in Q&A · Answered

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Thank you note

isa084 started May 9, 2026 in General

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Facing critical warnings and eroor while simulating the cva6 core on vivado

santoshmokashi86 asked Feb 25, 2026 in Q&A · Unanswered

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Genus synth of CVA6: empty module + feed-through/unloaded warnings — expected?

hareemrashid-arcanasemi asked Feb 16, 2026 in Q&A · Unanswered

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Undefined symbols for architecture arm64

jsjl3 asked Feb 5, 2026 in Q&A · Unanswered

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[l1 icache] cl_hit signal must be hot1

Leeconfig asked Nov 19, 2025 in Q&A · Unanswered

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Any interest in adding OpenROAD build support to cva6 repository

oharboe started Jul 13, 2025 in General · Closed

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Bottom 128 bits of icache data_sram unused

povik asked Jun 10, 2025 in Q&A · Answered

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Monitor instruction flowing into the pipeline through ILA on FPGA

gm-openchip asked Jun 10, 2025 in Q&A · Closed · Unanswered

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move MIMPID when bugs are fixed

bjdooks-ct started May 29, 2025 in Ideas

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When will the CV-X-IF interface support Memory Interface and Memory result interface?

NoahBraasch started May 19, 2025 in General

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H’vjh

olti30 started Apr 8, 2025 in Ideas

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How to get the design files separately to use for verification and synthesis in cadence or other tools

RakeshpatilLB asked Mar 25, 2025 in Q&A · Unanswered

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How to get the design files separately to use for verification and synthesis in cadence or other tools

RakeshpatilLB asked Mar 25, 2025 in Q&A · Unanswered

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QuestaSim flow

omahieux-oc started Feb 27, 2025 in General · Closed

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Add a peripheral with an interrupt source

librlib started Jan 14, 2025 in General

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Read/Write of Data in cache subsystem

Irsaliah asked Dec 12, 2024 in Q&A · Unanswered

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Required SRAM size for CVA6

AAnand-Git asked Sep 13, 2024 in Q&A · Unanswered

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Welcome to CVA6 Discussions!

zarubaf started Dec 14, 2020 in General

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Steps to run bare metal code on implemented CVA6 core

yadu-kr asked Dec 21, 2023 in Q&A · Unanswered

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Creating Vivado project

kristopher391 asked Sep 12, 2023 in Q&A · Unanswered

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Seeking explanation of some variable in Makefile!

AnikBalo asked Jun 8, 2023 in Q&A · Unanswered

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How can I generate VCD while performing cva6 rtl simulation in questasim?

AnikBalo asked May 23, 2023 in Q&A · Unanswered

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