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    • SystemVerilog
      0000Updated Nov 28, 2025Nov 28, 2025
    • landing

      Public
      TypeScript
      0000Updated Oct 27, 2025Oct 27, 2025
    • JavaScript
      MIT License
      2000Updated Sep 19, 2025Sep 19, 2025
    • SystemVerilog
      2000Updated Aug 4, 2025Aug 4, 2025
    • Jupyter Notebook
      Apache License 2.0
      1000Updated Jul 27, 2025Jul 27, 2025
    • SystemVerilog
      MIT License
      2000Updated Jul 26, 2025Jul 26, 2025
    • 2000Updated Jul 24, 2025Jul 24, 2025
    • HTML
      1000Updated Feb 19, 2025Feb 19, 2025
    • FPGA Project
      VHDL
      3000Updated Dec 22, 2024Dec 22, 2024
    • Repository with a list of FPGA student projects completed at Innopolis University during various courses
      0000Updated Oct 12, 2024Oct 12, 2024
    • River Raid game on FPGA
      Verilog
      3000Updated Oct 11, 2024Oct 11, 2024
    • project-schoolRISCV

      Public archive
      CPU microarchitecture, step by step
      Makefile
      Other
      68000Updated Oct 10, 2024Oct 10, 2024
    • Verilog
      1000Updated Dec 19, 2023Dec 19, 2023
    • SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course
      SystemVerilog
      MIT License
      1000Updated Dec 19, 2023Dec 19, 2023
    • project-SimpleCache

      Public archive
      Simple cache design implementation in verilog
      Verilog
      MIT License
      15000Updated Nov 20, 2023Nov 20, 2023
    • project-Game2048_FPGA

      Public archive
      Verilog
      1000Updated Jun 2, 2023Jun 2, 2023
    • SystemVerilog
      1000Updated Dec 12, 2022Dec 12, 2022
    • Stopwatch implementation for FPGA
      Verilog
      1000Updated Dec 10, 2022Dec 10, 2022
    • Verilog code for combinational lock on FPGA
      Verilog
      GNU General Public License v3.0
      3000Updated May 28, 2022May 28, 2022
    • 7-segment snake using a microcontroller
      SystemVerilog
      1000Updated Nov 15, 2019Nov 15, 2019
    • Computer Architecture course's project Fall 2018, Innopolis University.
      Verilog
      5000Updated Dec 6, 2018Dec 6, 2018
    • A snake game implemented in Verilog to run on FPGA
      Verilog
      3000Updated Dec 5, 2018Dec 5, 2018
    • project-Cube-Root

      Public archive
      CA project Fall 2018
      Verilog
      1000Updated Nov 14, 2018Nov 14, 2018
    • project-calculator

      Public archive
      CA project
      Verilog
      1000Updated Nov 14, 2018Nov 14, 2018
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