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    2 repositories

    • VerifEval

      Public
      SystemVerilog
      •3•11•1•1•Updated Sep 6, 2026Sep 6, 2026

    • apex-inference-chip

      Public
      An inference chip design that runs a real LLM (Qwen2.5-0.5B) on FPGA — one transformer decoder layer in RTL, every silicon value bit-exact against a golden mode…
      Python
      •
      Apache License 2.0
      •13•555•0•0•Updated Aug 18, 2026Aug 18, 2026
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