Our motivation to start this project is:
- Democratizing Hardware: We believe chip design should be accessible to everyone. This project aims to break down the barriers of expensive, proprietary EDA tools by providing a free, open-source flow from Verilog to GDS.
- Modernizing EDA: We're bringing a modern touch to EDA with a tool that is not only powerful and efficient but also intuitive to use, moving past outdated design philosophies.
- The Future is Open: The future of hardware development is open. This project fosters a collaborative ecosystem where innovation flourishes through transparency and community-driven development, rather than through closed-source solutions.
- High-performance C++ core optimized for speed and scalability
- Security and privacy-preserving design
- Integrates with leading open-source synthesis tools (e.g., Icarus Verilog, Yosys, ABC)
- Scalable and modular design for handling large VLSI design flows
- Boost (specifically, Boost.Asio)
- C++17 or later
- CMake 3.16 or later
mkdir build
cd build
cmake ..
make
./OstivalServer