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perf: decode only the span chains' coefficients in the Apple7/8 register decode tile - #20
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paperniuk merged 1 commit intoOct 21, 2026
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…ter decode tile The F32 span chains (MLX affine in groups of 64 or 128) read one coefficient per 64-input span, but the tile decoded one per 32-input group, two per span, each with its meta load and threadgroup store. The F32 instances of those formats now decode the coefficients their chains read alone, half the unit's. The Apple9 instances are unchanged. M2 Max, ms at one to four lanes: af4g64 17408x5120 gate/up 0.416 0.732 1.012 1.383 -> 0.404 0.724 1.004 1.360 af4g64 5120x17408 down 0.218 0.382 0.531 0.718 -> 0.212 0.377 0.528 0.710 af4g64 5120x6144 out 0.088 0.159 0.220 0.297 -> 0.086 0.158 0.219 0.294 af4g128 17408x5120 gate/up 0.405 0.726 1.010 1.364 -> 0.401 0.718 1.000 1.367 q4k (unchanged) within 0.2%
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This one is for MLX 4-bit, the default model. In the Apple7/8 F32 register decode tile, MLX affine 4-bit in groups of
64 (and 128) runs span chains: one chain per 64-input span, closed with one coefficient. The tile still decoded a
coefficient for every 32-input group, so half of them were decoded and never read, and each had its meta load and
threadgroup store. Removing them makes MLX 4-bit decode 2.8% faster at one lane on my M2 Max. As before, I used
Claude Code to author it and tested it by hand.
What changed
Only the Apple7/8 F32 instances of the register decode tile (
linear_gguf_sgmatrix.metal) change. Apple9 and hostcode are untouched.
SpanChain: MLX affine in groups of 64 or 128), the F32 instances decode only everyother coefficient of a unit, the ones the span chains read. The coefficient values and the chains are unchanged, so
the outputs are bit for bit the same.
gguf-projectionalready runs every format through the F32 instances: natively on Apple7/8, and onApple9+ through PR perf: zero points as mins and nibble operands in the Apple7/8 register decode tile #15's pass.
Results (M2 Max, 38-core GPU)
Kernel time,
gguf-projection-benchmark, at 1 / 2 / 3 / 4 lanes, ABBA order; Δ: − is faster.MLX 4-bit on the M2 Max, before and after
make test-performance-real,mlx-community/Qwen3.8-27B-4bit, ANE share 0.35. Times in seconds; decode in tok/s.Prefill doesn't change: the change is decode-only, and prefill runs the staged MMA tile. Three MLX runs of this branch
agree within 0.3%.
Testing
gguf-projectionpasses on the M2 Max (all 43 formats, F32 instances natively).make checkpasses on the M2 Max.make test-performance-realwith MLX 4-bit, before and after.