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STMPi15 Mini

Compact embedded Linux SBC based on STM32MP157A SoC with RPi-like form factor but smaller (72×46mm), built for lightweight headless workloads. Designed with LCSC components for full JLCPCB assembly, shared as an EasyEDA Pro project file + Buildroot SDK.

License: Hardware designs under CERN-OHL-P-2.0. Other components may have different licenses - see LICENSE for details.

Disclaimer: Still WIP, use at your own risk.

RPi 5 & STMPi15 Mini

The STMicro STM32MP15 is a line of application processors (a.k.a. MPU) based on ARM Cortex-A7 32-bit cores that feature :

  • Very low power consumption (~1W-ish) & heat dissipation (runs without heatsink or fan)
  • Proper docs, active support, reliable supply
  • Up-to-date & well-maintained Linux BSP (currently kernel 6.6)
  • Heterogeneous architecture (dual A7 + M4) capable to handle both Linux workloads and hard real-time tasks without an external MCU
  • DDR3 support ("cheap" & easy to route up to 1GB)
  • 0.8mm pitch BGA package option = no HDI required

The board currently runs a minimal Linux distro built with the Buildroot toolchain, based on DT & config files from the official Bootlin's buildroot-external-st tree and examples. A typical image boots to userspace in ~5 sec with ~20MB RAM used idle.


Hardware specifications

SoC STM32MP157AAB3 (LFBGA354)
Main CPU 2× Cortex-A7 @ 650MHz
Real-time core Cortex-M4 @ 209MHz with FPU
RAM 512MB DDR3L @ 533 MHz
Storage 512MB QSPI NAND Flash + MicroSD slot
Ethernet 1× 100Mbps (WCH CH182D PHY), RJ45 jack
USB 1× device w/ power input (USB-C) + 1× host (USB-A)
Display MIPI DSI (RPi-compatible 15-pin connector)
GPIO 30-pin header - pinout
Size 72 × 46 mm
Power ~0.5W idle, ~1.2W load

The board is drop-in compatible with other chips of the STM32MP15 family, featuring 1 or 2 A7 cores, various Ethernet/CAN/display options, 650 or 800MHz CPU clock and optional crypto hardware. See ST's website for full product line introduction, and the SoC compatibility section below for what to watch when swapping chips.

On top of the usual UART/I2C/SPI/PWMs, the STM32MP157 packs other useful peripherals: 2× CAN FD controllers, 2× 16-bit ADCs, 2× 12-bit DACs, hardware RTC, 2× independent watchdogs (IWDG), internal temperature sensor, TrustZone security, and a Vivante GPU for 2D/3D acceleration. Low-power modes (Sleep, Stop, Standby) are available but not leveraged on this board, it's an always-on design with fixed CPU voltage.


Design highlights

PCB 3D rendering

  • Switchable USB host: The USB host port can be routed to either the USB-A connector (default) or a parallel MX 1.25mm wire-to-board connector, via TS3USB221A analog mux controlled by a GPIO. This lets shields carry their own USB peripherals (WiFi/4G modem, sound card, storage, Ethernet port/switch...) without external cables. Works fine at USB 2.0 HS speeds.

  • Flat top surface: LEDs reverse-mounted (shine through PCB), RESET button side-mounted on bottom. Shields can place connectors at the edge with ~11mm clearance.

  • RPi-compatible DSI: 15-pin FPC pinout matches Raspberry Pi. Most RPi DSI displays should work without hardware hacks, just the FPC cable for video + I2C touch. Driver support may vary. DSI power out (3V3) is supplied through AP22814 load switch controlled by a GPIO.

  • DIP switch boot source: 3-position switch selects boot from QSPI NAND, SD card or USB DFU/UART

  • Dedicated debug UART: Terminal block for UART4 (console).

  • Backpower protection: Schottky diode on USB 5V input prevents backfeeding the host connected to USB-C port when powered from GPIO pin header.

  • Debug pads on back: SWD/JTAG signals (SWDIO, SWCLK, nRST, SWO) exposed as 1.5mm pads for pogo pins or soldering. Power rail test points included.


Pin mapping

The diagram shows default pin functions. Most pins support alternate functions - see STM32MP157 datasheet for full pinmux options.

GPIO Header Pinout Generated with pinoutleaf

  • Debug UART: UART4 on terminal block — PG11 (TX), PB2 (RX)
  • Internal signals: LED, USB mux, PHY reset, etc. — details

PCB design

6-layer stackup (JLC06161H-3313): Sig/GND⸺GND/Sig⸺GND/Sig pattern. Power as fat traces + VCC_DDR polygon, no dedicated power plane. All signals have continuous GND reference (or VCC_DDR for A/C signals routed on inner layer).

Layer Content
Top Signals (DDR, peripherals), connectors
L2 GND plane (solid)
L3 GND plane + VCC_DDR area under RAM
L4 Signals + power traces
L5 GND plane (solid)
Bottom Signals + power traces

DDR layout: The SoC is rotated vs ST's reference design to fit the compact form factor, which forces DDR signals across 3 layers (Top, L4, Bottom) instead of 2. Time-matching compensates for different propagation speeds: inner layer traces are ~14% shorter than outer layers. A standalone DDR test suite (based on ST's STM32DDRFW-UTIL) is included to validate the memory interface during bringup - useful to confirm signal integrity and timing margins before attempting to boot Linux.

Double-sided assembly: Components on both faces. JLCPCB-assemblable with standard process.

Discrete power: No PMIC - individual buck converters for VCC_3V3 (3.3V), VCC_DDR (1.35V), and VDD_CPU (1.215V). Sequencing handled by the MPU internally; EN pins of DDR/CPU bucks tied to PWR_ON + nRST, small RC delay on VCC_3V3. A load switch gates USB PHY power until 1V8 is stable (ST requirement).

Flush SD slot: Push-pull connector positions the card above bottom-layer components. Not accessible from outside, intended for permanent internal storage, not hot-swap.

External 24MHz HSE: Crystal oscillator for accurate clocking. No reliance on internal RC.

No VBAT connector: RTC backup not exposed - internally connected to 3V3, keeps the board simple.


SoC compatibility

The board is pin-compatible with the full STM32MP15x family. Key points when swapping chips:

  • -D/-F variants (800MHz): Require 1.34V on VDD_CPU instead of 1.215V - adjust buck divider resistors
  • MP153: No MIPI DSI
  • MP151: No MIPI DSI, no CAN
  • -C/-F variants: Hardware crypto available (CRYP, HASH, RNG) - requires DTS + kernel config

See ST's AN5031 for full hardware development guidelines.


Boot config

Boot source selected via 3-position DIP switch (from ST docs):

Boot modes

  • QSPI NAND for boot (TF-A + FIP + kernel + rootfs) - soldered, reliable, fast enough for this class of application
  • SD card for additional storage (logs, config, data) - not recommended for critical data since it's removable and less reliable. Useful during bringup to iterate quickly on Linux images.

Software

The sdk/ folder contains a BR2_EXTERNAL tree to build a complete Linux image for this board. It's a homemade BSP based on ST's device trees, with the appropriate bootchain versions (TF-A, OP-TEE, U-Boot) and kernel 6.6. Device tree patches are adapted for the MP157 and this specific board layout.

Tested with Buildroot 2025.02.5. Should work with newer releases - the BR2_EXTERNAL only overrides board-specific bits, everything else comes from upstream Buildroot + ST's official patches.

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Custom embedded mini SBC based on STM32MP15

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