UART receiver

[Aleksei-Fil]

Можно посмотреть тест по tb с помощью команд
iverilog -o sim tb.v uart_rx.v
vvp sim
gtkwave uart_tx_tb.vcd
В файле топ сделаны тестовые выводы на led для 8, 4, 2, 6.

[pointcheck]

Почему удален модуль uart_transmitter ?

[pointcheck]

Выявлены следющие проблемы:

1. В tb есть синтаксическая ошибка:

rz@butterfly:~/test/learning-fpga/uart_receiver % iverilog -o sim tb.v uart_rx.v
tb.v:25: error: port ``output_rx_data'' is not a port of uut.
1 error(s) during elaboration.

2. После того как я её исправил, tb все равно не проходит:

rz@butterfly:~/test/learning-fpga/uart_receiver % vvp sim
VCD info: dumpfile uart_rx_tb.vcd opened for output.
Time =                    0 ns: state = 0, rx_data = 00, parity_valid = 1, ready = 1
Sending 'A' (0x41)
Time =               220000 ns: state = 1, rx_data = 00, parity_valid = 1, ready = 0
Time =              4580000 ns: state = 2, rx_data = 00, parity_valid = 1, ready = 0
Time =             13260000 ns: state = 2, rx_data = 01, parity_valid = 0, ready = 0
Time =             65340000 ns: state = 2, rx_data = 41, parity_valid = 1, ready = 0
Time =             74020000 ns: state = 3, rx_data = 41, parity_valid = 1, ready = 0
Time =             82700000 ns: state = 4, rx_data = 41, parity_valid = 1, ready = 0
Time =             91380000 ns: state = 0, rx_data = 41, parity_valid = 1, ready = 1
Time =             91420000 ns: state = 0, rx_data = 00, parity_valid = 1, ready = 1
Test 1 FAILED
Sending 'B' (0x42)
Time =            147780000 ns: state = 1, rx_data = 00, parity_valid = 1, ready = 0
Time =            152140000 ns: state = 2, rx_data = 00, parity_valid = 1, ready = 0
Time =            169500000 ns: state = 2, rx_data = 02, parity_valid = 0, ready = 0
Time =            212900000 ns: state = 2, rx_data = 42, parity_valid = 1, ready = 0
Time =            221580000 ns: state = 3, rx_data = 42, parity_valid = 1, ready = 0
Time =            230260000 ns: state = 4, rx_data = 42, parity_valid = 1, ready = 0
Time =            238940000 ns: state = 0, rx_data = 42, parity_valid = 1, ready = 1
Time =            238980000 ns: state = 0, rx_data = 00, parity_valid = 1, ready = 1
Test 2 FAILED
tb.v:117: $finish called at 347400000 (1ps)

Логическая ошибка находится в модуле uart_rx. Её видно на выводе от tb, попробуй разобраться самостоятельно.

Выявлены ошибки в модуле uart_rx и в tb.