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Fix FPGA synthesizability #34

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Fix FPGA synthesizability #34

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26f6818
Use FF-based input buffer when targeting FPGA
LuigiGhionda Jun 2, 2025
01ff0f5
rtl: Move wildcard imports to module header
alex96295 Jun 2, 2025
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3 changes: 1 addition & 2 deletions rtl/accumulator/neureka_accumulator_adder.sv
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Expand Up @@ -20,9 +20,8 @@
* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_accumulator_adder #(
module neureka_accumulator_adder import neureka_package::*; #(
parameter int unsigned NADD = neureka_package::NEUREKA_TP_OUT,
parameter int unsigned ACC = neureka_package::NEUREKA_ACCUM_SIZE,
parameter int unsigned QNT = 32,
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3 changes: 1 addition & 2 deletions rtl/accumulator/neureka_accumulator_normquant.sv
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* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_accumulator_normquant #(
module neureka_accumulator_normquant import neureka_package::*; #(
parameter int unsigned TP = NEUREKA_TP_IN, // output filter size in bits/cycle
parameter int unsigned AP = NEUREKA_TP_OUT, // number of accumulators
parameter int unsigned ACC = NEUREKA_ACCUM_SIZE,
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3 changes: 1 addition & 2 deletions rtl/accumulator/neureka_normquant.sv
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* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_normquant #(
module neureka_normquant import neureka_package::*; #(
parameter int unsigned NMULT = 4,
parameter int unsigned NMS = neureka_package::NORM_MULT_SIZE,
parameter int unsigned ACC = neureka_package::NEUREKA_ACCUM_SIZE,
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4 changes: 1 addition & 3 deletions rtl/accumulator/neureka_normquant_bias.sv
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* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;


module neureka_normquant_bias #(
module neureka_normquant_bias import neureka_package::*; #(
parameter int unsigned NADD = 8,
parameter int unsigned ACC = neureka_package::NEUREKA_ACCUM_SIZE,
parameter int unsigned QNT = 32,
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3 changes: 1 addition & 2 deletions rtl/accumulator/neureka_normquant_multiplier.sv
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* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_normquant_multiplier #(
module neureka_normquant_multiplier import neureka_package::*; #(
parameter int unsigned NMS = neureka_package::NORM_MULT_SIZE,
parameter int unsigned ACC = neureka_package::NEUREKA_ACCUM_SIZE,
parameter int unsigned PIPE = 0
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3 changes: 1 addition & 2 deletions rtl/accumulator/neureka_normquant_shifter.sv
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* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_normquant_shifter #(
module neureka_normquant_shifter import neureka_package::*; #(
parameter int unsigned ACC = neureka_package::NEUREKA_ACCUM_SIZE,
parameter int unsigned INT = 33,
parameter int unsigned OUTPUT_REGISTER = 0
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3 changes: 1 addition & 2 deletions rtl/array/neureka_binconv_array.sv
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Expand Up @@ -20,9 +20,8 @@
* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_binconv_array #(
module neureka_binconv_array import neureka_package::*; #(
parameter int unsigned COLUMN_SIZE = NEUREKA_COLUMN_SIZE, // number of BinConv blocks per column (default 9)
parameter int unsigned NR_PE = NEUREKA_PE_HW_DEFAULT, // number of BinConv columns (default 9 -- same of size of BinConv columns!)
parameter int unsigned BLOCK_SIZE = NEUREKA_BLOCK_SIZE, // number of SoP's per BinConv block (default 4)
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3 changes: 1 addition & 2 deletions rtl/array/neureka_binconv_col.sv
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Expand Up @@ -19,9 +19,8 @@
* Authors (NE16): Francesco Conti <francesco.conti@greenwaves-technologies.com>
* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/
import neureka_package::*;

module neureka_binconv_column #(
module neureka_binconv_column import neureka_package::*; #(
parameter int unsigned BLOCK_SIZE = NEUREKA_BLOCK_SIZE,
parameter int unsigned COLUMN_SIZE= NEUREKA_COLUMN_SIZE,
parameter int unsigned TP_IN = NEUREKA_TP_IN,
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3 changes: 1 addition & 2 deletions rtl/array/neureka_binconv_pe.sv
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* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_binconv_pe #(
module neureka_binconv_pe import neureka_package::*; #(
parameter int unsigned COLUMN_SIZE = NEUREKA_COLUMN_SIZE, // number of BinConv blocks per column (default 9)
parameter int unsigned BLOCK_SIZE = NEUREKA_BLOCK_SIZE, // number of Binconv per block
parameter int unsigned BC_COLBLOCK_SIZE = COLUMN_SIZE*BLOCK_SIZE, // total number of binconv per PE
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3 changes: 1 addition & 2 deletions rtl/array/neureka_scale.sv
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Expand Up @@ -20,9 +20,8 @@
* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_scale #(
module neureka_scale import neureka_package::*; #(
parameter int unsigned INP_ACC = 8, // input bitwidth
parameter int unsigned OUT_ACC = 16, // output bitwidth
parameter int unsigned N_SHIFTS = 8 // number of mutliplexed shifts
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6 changes: 4 additions & 2 deletions rtl/ctrl/neureka_ctrl.sv
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Expand Up @@ -20,11 +20,13 @@
* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

`include "register_interface/typedef.svh"

module neureka_ctrl
import neureka_package::*;
import hwpe_ctrl_package::*;
import hci_package::*;

module neureka_ctrl #(
#(
parameter int unsigned N_CORES = NR_CORES,
parameter int unsigned ID = ID_WIDTH,
parameter int unsigned PE_H = NEUREKA_PE_H_DEFAULT,
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3 changes: 1 addition & 2 deletions rtl/ctrl/neureka_ctrl_fsm.sv
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* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

module neureka_ctrl_fsm
import neureka_package::*;
import hwpe_ctrl_package::*;
import hci_package::*;

module neureka_ctrl_fsm
#(
parameter int unsigned NUM_PE = NEUREKA_NUM_PE_MAX
)
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3 changes: 1 addition & 2 deletions rtl/input_buffer/neureka_double_input_buffer.sv
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* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_double_infeat_buffer #(
module neureka_double_infeat_buffer import neureka_package::*; #(
parameter int unsigned INPUT_BUF_SIZE = 2048,
parameter int unsigned BLOCK_SIZE = NEUREKA_BLOCK_SIZE,
parameter int unsigned DW = NEUREKA_QA_IN,
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16 changes: 11 additions & 5 deletions rtl/input_buffer/neureka_input_buffer.sv
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Expand Up @@ -20,9 +20,8 @@
* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_infeat_buffer #(
module neureka_infeat_buffer import neureka_package::*; #(
parameter int unsigned INPUT_BUF_SIZE = 2048,
parameter int unsigned BLOCK_SIZE = NEUREKA_BLOCK_SIZE,
parameter int unsigned DW = NEUREKA_QA_IN,
Expand Down Expand Up @@ -54,6 +53,12 @@ module neureka_infeat_buffer #(
localparam AW = $clog2(NW);
localparam DS = DW*BLOCK_SIZE;

`ifdef TARGET_FPGA
localparam NEUREKA_BUFFER = neureka_package::BUFFER_FF;
`else
localparam NEUREKA_BUFFER = neureka_package::BUFFER_LATCHES;
`endif

// Standard-cell memory based feature register
logic scm_re;
logic [AW-1:0] scm_raddr;
Expand All @@ -71,9 +76,10 @@ module neureka_infeat_buffer #(
logic [AW-1:0] vlen_cnt_fast_d, vlen_cnt_fast_q;

neureka_infeat_buffer_scm_test_wrap #(
.ADDR_WIDTH ( AW ),
.DATA_WIDTH ( DS ),
.NUM_WORDS ( NW )
.ADDR_WIDTH ( AW ),
.DATA_WIDTH ( DS ),
.NUM_WORDS ( NW ),
.USE_LATCHES ( NEUREKA_BUFFER )
) i_infeat_buffer_scm (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
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3 changes: 1 addition & 2 deletions rtl/input_buffer/neureka_input_buffer_newer.sv
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Expand Up @@ -20,9 +20,8 @@
* Authors (NEUREKA): Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
*/

import neureka_package::*;

module neureka_infeat_buffer #(
module neureka_infeat_buffer import neureka_package::*; #(
parameter int unsigned INPUT_BUF_SIZE = 2048,
parameter int unsigned BLOCK_SIZE = NEUREKA_BLOCK_SIZE,
parameter int unsigned DW = NEUREKA_QA_IN
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73 changes: 43 additions & 30 deletions rtl/input_buffer/neureka_input_buffer_scm.sv
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Expand Up @@ -24,7 +24,8 @@ module neureka_infeat_buffer_scm
#(
parameter int unsigned ADDR_WIDTH = 6,
parameter int unsigned DATA_WIDTH = 128,
parameter int unsigned NUM_WORDS = 64
parameter int unsigned NUM_WORDS = 64,
parameter int unsigned USE_LATCHES = 0
)
(
input logic clk_i,
Expand All @@ -48,31 +49,33 @@ module neureka_infeat_buffer_scm

// Read address register, located at the input of the address decoder
logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] buffer;
logic [NUM_WORDS-1:0] waddr_onehot;
logic [NUM_WORDS-1:0] clk_we;

logic [DATA_WIDTH-1:0] wdata_q;

// ========================================================================
// WDATA SAMPLING
// ========================================================================
always_ff @(posedge clk_i or negedge rst_ni)
begin
if(~rst_ni)
wdata_q <= '0;
else if(clear_i)
wdata_q <= '0;
else if(we_i)
wdata_q <= wdata_i;
end

// ========================================================================
// SCM (LATCHES)
// ========================================================================
if(USE_LATCHES) begin : gen_latches

logic [NUM_WORDS-1:0] waddr_onehot;
logic [NUM_WORDS-1:0] clk_we;

logic [DATA_WIDTH-1:0] wdata_q;

// ========================================================================
// WDATA SAMPLING
// ========================================================================
always_ff @(posedge clk_i or negedge rst_ni)
begin
if(~rst_ni)
wdata_q <= '0;
else if(clear_i)
wdata_q <= '0;
else if(we_i)
wdata_q <= wdata_i;
end

// use the sampled address to select the correct rdata_o
// decode
generate
// ========================================================================
// SCM (LATCHES)
// ========================================================================

// use the sampled address to select the correct rdata_o
// decode
for(genvar ii=0; ii<NUM_WORDS; ii++) begin : WADDR_DECODE

always_comb
Expand All @@ -86,10 +89,8 @@ module neureka_infeat_buffer_scm
end

end
endgenerate

// generate one clock-gating cell for each register element
generate
// generate one clock-gating cell for each register element
for(genvar ii=0; ii<NUM_WORDS; ii++) begin : CG_CELL_WORD_ITER

cluster_clock_gating i_cg
Expand All @@ -101,9 +102,7 @@ module neureka_infeat_buffer_scm
);

end
endgenerate

generate

for(genvar ii=0; ii<NUM_WORDS; ii++) begin : LATCH

Expand All @@ -116,7 +115,21 @@ module neureka_infeat_buffer_scm

end

endgenerate
end else begin : gen_ff

always_ff @(posedge clk_i or negedge rst_ni)
begin
if(~rst_ni)
for (int i = 0; i < NUM_WORDS; i++)
buffer[i] <= '0;
else if(clear_i)
for (int i = 0; i < NUM_WORDS; i++)
buffer[i] <= '0;
else if(we_i)
buffer[waddr_i] <= wdata_i;
end

end

assign infeat_buffer_o = buffer;

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10 changes: 6 additions & 4 deletions rtl/input_buffer/neureka_input_buffer_scm_test_wrap.sv
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Expand Up @@ -24,7 +24,8 @@ module neureka_infeat_buffer_scm_test_wrap
#(
parameter int unsigned ADDR_WIDTH = 6,
parameter int unsigned DATA_WIDTH = 128,
parameter int unsigned NUM_WORDS = 64
parameter int unsigned NUM_WORDS = 64,
parameter int unsigned USE_LATCHES = 0
)
(
input logic clk_i,
Expand Down Expand Up @@ -100,9 +101,10 @@ module neureka_infeat_buffer_scm_test_wrap

neureka_infeat_buffer_scm
#(
.ADDR_WIDTH ( ADDR_WIDTH ),
.DATA_WIDTH ( DATA_WIDTH ),
.NUM_WORDS ( NUM_WORDS )
.ADDR_WIDTH ( ADDR_WIDTH ),
.DATA_WIDTH ( DATA_WIDTH ),
.NUM_WORDS ( NUM_WORDS ),
.USE_LATCHES ( USE_LATCHES )
)
neureka_infeat_buffer_scm_i
(
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4 changes: 1 addition & 3 deletions rtl/neureka_engine.sv
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Expand Up @@ -21,9 +21,7 @@
* Francesco Conti <f.conti@unibo.it>
*/

import neureka_package::*;

module neureka_engine #(
module neureka_engine import neureka_package::*; #(
parameter int unsigned COLUMN_SIZE = NEUREKA_COLUMN_SIZE, // number of BinConv blocks per column (default 9)
parameter int unsigned BLOCK_SIZE = NEUREKA_BLOCK_SIZE, // number of SoP's per BinConv block (default 4),
parameter int unsigned TP_IN = NEUREKA_TP_IN, // number of input elements processed per cycle
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5 changes: 5 additions & 0 deletions rtl/neureka_package.sv
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Expand Up @@ -145,6 +145,11 @@ package neureka_package;
flags_infeat_buffer_t flags_even_infeat_buffer;
} flags_double_infeat_buffer_t;

typedef enum integer {
BUFFER_FF = 0,
BUFFER_LATCHES = 1
} regfile_e;


// ========================================================================
// SIGN_BUFFER related types
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