Add HMR unit

.github/waiver.verible

@@ -3,3 +3,4 @@
 # SPDX-License-Identifier: SHL-0.51
 
 waive --rule=explicit-parameter-storage-type --location="./rtl/ecc_wrap/ecc_sram.sv"
+waive --rule=module-filename --location="./rtl/HMR/recovery_rf_latch.sv"

.github/workflows/ci.yml

@@ -51,6 +51,14 @@ jobs:
             ./rtl/ecc_wrap/ecc_manager_reg_top.sv
             ./rtl/ODRG_unit/odrg_manager_reg_pkg.sv
             ./rtl/ODRG_unit/odrg_manager_reg_top.sv
+            ./rtl/HMR/hmr_core_regs_reg_pkg.sv
+            ./rtl/HMR/hmr_core_regs_reg_top.sv
+            ./rtl/HMR/hmr_dmr_regs_reg_pkg.sv
+            ./rtl/HMR/hmr_dmr_regs_reg_top.sv
+            ./rtl/HMR/hmr_registers_reg_pkg.sv
+            ./rtl/HMR/hmr_registers_reg_top.sv
+            ./rtl/HMR/hmr_tmr_regs_reg_pkg.sv
+            ./rtl/HMR/hmr_tmr_regs_reg_top.sv
             ./rtl/pulpissimo_tcls/tcls_manager_reg_pkg.sv
             ./rtl/pulpissimo_tcls/tcls_manager_reg_top.sv
           extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal --waiver_files .github/waiver.verible"

Bender.yml

@@ -20,6 +20,19 @@ sources:
   - rtl/ODRG_unit/odrg_manager_reg_pkg.sv
   - rtl/ecc_wrap/ecc_manager_reg_pkg.sv
   - rtl/pulpissimo_tcls/tcls_manager_reg_pkg.sv
+  - rtl/lowrisc_ecc/prim_secded_13_8_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_13_8_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_13_8_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_22_16_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_22_16_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_22_16_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_39_32_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_39_32_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_39_32_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_72_64_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_72_64_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_72_64_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_pkg.sv
   - rtl/ODRG_unit/triple_core_barrier.sv
   - rtl/hsiao_ecc/hsiao_ecc_pkg.sv
   - rtl/hsiao_ecc/hsiao_ecc_enc.sv
@@ -28,6 +41,7 @@ sources:
   - rtl/TMR_voter.sv
   - rtl/TMR_voter_fail.sv
   - rtl/TMR_word_voter.sv
+  - rtl/HMR/resp_suppress.sv
     # Level 1
   - rtl/ODRG_unit/odrg_manager_reg_top.sv
   - rtl/ecc_wrap/ecc_manager_reg_top.sv
@@ -103,6 +117,30 @@ sources:
       - test/tb_bitwise_tmr_voter_fail.sv
       - test/tb_voter_macros.sv
 
+  - files:
+      - rtl/HMR/rapid_recovery_pkg.sv
+      - rtl/HMR/recovery_csr.sv
+      - rtl/HMR/recovery_pc.sv
+      - rtl/HMR/recovery_rf.sv
+      - rtl/HMR/rapid_recovery_unit.sv
+      - rtl/HMR/DMR_checker.sv
+      - rtl/HMR/DMR_CSR_checker.sv
+      - rtl/HMR/DMR_address_generator.sv
+      # - rtl/HMR/DMR_controller.sv
+      - rtl/HMR/hmr_rapid_recovery_ctrl.sv
+      - rtl/HMR/hmr_registers_reg_pkg.sv
+      - rtl/HMR/hmr_core_regs_reg_pkg.sv
+      - rtl/HMR/hmr_dmr_regs_reg_pkg.sv
+      - rtl/HMR/hmr_tmr_regs_reg_pkg.sv
+      - rtl/HMR/hmr_registers_reg_top.sv
+      - rtl/HMR/hmr_core_regs_reg_top.sv
+      - rtl/HMR/hmr_dmr_regs_reg_top.sv
+      - rtl/HMR/hmr_dmr_ctrl.sv
+      - rtl/HMR/hmr_tmr_regs_reg_top.sv
+      - rtl/HMR/hmr_tmr_ctrl.sv
+      - rtl/HMR/HMR_wrap.sv
+      - rtl/HMR/hmr_unit.sv
+
 vendor_package:
   - name: lowrisc_opentitan
     target_dir: "util/lowrisc_opentitan"

CHANGELOG.md

@@ -11,7 +11,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Changed
 - Replace vendor.py script with bender vendor for ECC modules
 - Update `ecc_manager` for configurability
-- Update secded testbench to use correctors and fix error injection
 
 ## 0.5.1 - 2023-04-12
 ### Added
@@ -29,11 +28,13 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Expose additional error logging signals
 - Add scrubber to ECC SRAM wrap
 - Add testing signals for tapeout
+- Add secded ECC corrector
 
 ### Changed
 - Expose  `ecc_sram` ecc error signals
 - Rename cTCLS to ODRG
 - Hide bus ecc behind bender targets, remove related dependencies
+- Update secded testbench to use correctors and fix error injection
 
 ## 0.4.0 - 2022-03-31
 

Makefile

@@ -22,12 +22,60 @@ REG_TOOL = $(REG_PATH)/vendor/lowrisc_opentitan/util/regtool.py
 
 HJSON_ODRG = rtl/ODRG_unit/ODRG_unit.hjson
 HJSON_TCLS = rtl/pulpissimo_tcls/TCLS_unit.hjson
+HJSON_HMR = rtl/HMR/HMR_regs.hjson
+HJSON_HMR_core = rtl/HMR/HMR_core_regs.hjson
+HJSON_HMR_dmr = rtl/HMR/HMR_dmr_regs.hjson
+HJSON_HMR_tmr = rtl/HMR/HMR_tmr_regs.hjson
 HJSON_ECC = rtl/ecc_wrap/ecc_sram_wrapper.hjson
 
 TARGET_DIR_ODRG = rtl/ODRG_unit
 TARGET_DIR_TCLS = rtl/pulpissimo_tcls
+TARGET_DIR_HMR = rtl/HMR
 TARGET_DIR_ECC = rtl/ecc_wrap
 
+define HMR_H_HEADER_STRING
+/*
+ * Copyright (C) 2023 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARCHI_HMR_HMR_V1_H__
+#define __ARCHI_HMR_HMR_V1_H__
+
+#define HMR_IN_INTERLEAVED 1
+
+#define HMR_TOP_OFFSET 0x000
+#define HMR_CORE_OFFSET   0x100
+#define HMR_DMR_OFFSET    0x200
+#define HMR_TMR_OFFSET    0x300
+
+#define HMR_CORE_INCREMENT 0x010
+#define HMR_CORE_SLL       0x004
+#define HMR_DMR_INCREMENT  0x010
+#define HMR_DMR_SLL        0x004
+#define HMR_TMR_INCREMENT  0x010
+#define HMR_TMR_SLL        0x004
+\n
+endef
+define HMR_H_FINAL_STRING
+\n\n
+#endif // __ARCHI_HMR_HMR_V1_H__
+
+endef
+export HMR_H_HEADER_STRING
+export HMR_H_FINAL_STRING
+
 .PHONY: gen_ODRG gen_TCLS gen_ecc_registers gen_ECC
 gen_ODRG:
 	python $(REG_TOOL) $(HJSON_ODRG) -t $(TARGET_DIR_ODRG) -r
@@ -39,6 +87,24 @@ gen_TCLS:
 	python $(REG_TOOL) $(HJSON_TCLS) -d > $(TARGET_DIR_TCLS)/doc.md
 	python $(REG_TOOL) $(HJSON_TCLS) -D > $(TARGET_DIR_TCLS)/TCLS.h
 
+gen_HMR:
+	python $(REG_TOOL) $(HJSON_HMR) -t $(TARGET_DIR_HMR) -r
+	python $(REG_TOOL) $(HJSON_HMR) -d > $(TARGET_DIR_HMR)/doc.html
+	python $(REG_TOOL) $(HJSON_HMR) --doc > $(TARGET_DIR_HMR)/doc.md
+	python $(REG_TOOL) $(HJSON_HMR_core) -t $(TARGET_DIR_HMR) -r
+	python $(REG_TOOL) $(HJSON_HMR_dmr) -t $(TARGET_DIR_HMR) -r
+	python $(REG_TOOL) $(HJSON_HMR_tmr) -t $(TARGET_DIR_HMR) -r
+
+	@printf "$$HMR_H_HEADER_STRING" > $(TARGET_DIR_HMR)/hmr_v1.h
+	python $(REG_TOOL) $(HJSON_HMR) -D >> $(TARGET_DIR_HMR)/hmr_v1.h
+	@printf "\n\n" >> $(TARGET_DIR_HMR)/hmr_v1.h
+	python $(REG_TOOL) $(HJSON_HMR_core) -D >> $(TARGET_DIR_HMR)/hmr_v1.h
+	@printf "\n\n" >> $(TARGET_DIR_HMR)/hmr_v1.h
+	python $(REG_TOOL) $(HJSON_HMR_dmr) -D >> $(TARGET_DIR_HMR)/hmr_v1.h
+	@printf "\n\n" >> $(TARGET_DIR_HMR)/hmr_v1.h
+	python $(REG_TOOL) $(HJSON_HMR_tmr) -D >> $(TARGET_DIR_HMR)/hmr_v1.h
+	@printf "$$HMR_H_FINAL_STRING" >> $(TARGET_DIR_HMR)/hmr_v1.h
+
 gen_ecc_registers:
 	python $(REG_TOOL) $(HJSON_ECC) -t $(TARGET_DIR_ECC) -r
 	python $(REG_TOOL) $(HJSON_ECC) -d > $(TARGET_DIR_ECC)/doc.md

rtl/HMR/DMR_CSR_checker.sv

@@ -0,0 +1,51 @@
+/* Copyright 2020 ETH Zurich and University of Bologna.
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the "License"); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * CS Registers Checker
+ *
+ */
+
+module DMR_CSR_checker
+  import rapid_recovery_pkg::*;
+(
+  input  csrs_intf_t csr_a_i,
+  input  csrs_intf_t csr_b_i,
+  output csrs_intf_t check_o,
+  output logic       error_o
+);
+
+logic compare_mstatus;
+logic compare_mie;
+logic compare_mtvec;
+logic compare_mscratch;
+logic compare_mip;
+logic compare_mepc;
+logic compare_mcause;
+logic error;
+
+assign compare_mstatus = |(csr_a_i.csr_mstatus ^ csr_b_i.csr_mstatus);
+assign compare_mie = |(csr_a_i.csr_mie ^ csr_b_i.csr_mie);
+assign compare_mtvec = |(csr_a_i.csr_mtvec ^ csr_b_i.csr_mtvec);
+assign compare_mscratch = |(csr_a_i.csr_mscratch ^ csr_b_i.csr_mscratch);
+assign compare_mip = |(csr_a_i.csr_mip ^ csr_b_i.csr_mip);
+assign compare_mepc = |(csr_a_i.csr_mepc ^ csr_b_i.csr_mepc);
+assign compare_mcause = |(csr_a_i.csr_mcause ^ csr_b_i.csr_mcause);
+
+assign error = compare_mstatus  |
+               compare_mie      |
+               compare_mtvec    |
+               compare_mscratch |
+               compare_mip      |
+               compare_mepc     |
+               compare_mcause;
+assign check_o = (error) ? csr_a_i : '0;
+assign error_o = error;
+
+endmodule : DMR_CSR_checker

rtl/HMR/DMR_address_generator.sv

@@ -0,0 +1,71 @@
+/* Copyright 2020 ETH Zurich and University of Bologna.
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the "License"); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * Dual Modular Address Generator
+ * Generates addresses for RF refill
+ *
+ */
+
+module DMR_address_generator #(
+  parameter  int unsigned AddrWidth = 5
+)(
+  input  logic                 clk_i    ,
+  input  logic                 rst_ni   ,
+  input  logic                 clear_i  ,
+  input  logic                 enable_i ,
+  output logic                 done_o   ,
+  output logic                 fatal_o  ,
+  output logic [AddrWidth-1:0] address_o
+);
+
+localparam int unsigned NumAddr = 2 ** (AddrWidth - 1);
+localparam int unsigned NumVotingSignals = 3;
+localparam int unsigned NumTMRResults = 1;
+localparam int unsigned ArrayWidth = NumVotingSignals + NumTMRResults;
+
+logic addr_count_err;
+logic [NumVotingSignals-1:0] addr_count_rst;
+logic [ArrayWidth-1:0][AddrWidth-1:0] addr_count;
+
+generate
+  for (genvar i = 0; i < NumVotingSignals; i++) begin : gen_addr_ffs
+    always_ff @(posedge clk_i, negedge  rst_ni) begin : address_generator_counter
+      if (~rst_ni)
+        addr_count [i] <= '1;
+      else begin
+        if (clear_i || addr_count_rst [i])
+          addr_count [i] <= '1;
+        else if (enable_i)
+          addr_count [i] <= addr_count [i] + 1;
+        else
+          addr_count [i] <= addr_count [i];
+      end
+    end
+  assign addr_count_rst [i] = ( addr_count [i] == NumAddr/2 - 1) ? 1'b1 : 1'b0;
+  end
+endgenerate
+
+bitwise_TMR_voter #(
+  .DataWidth ( AddrWidth ),
+  .VoterType ( 0         )
+) address_counter_voter (
+  .a_i         ( addr_count [0] ),
+  .b_i         ( addr_count [1] ),
+  .c_i         ( addr_count [2] ),
+  .majority_o  ( addr_count [3] ),
+  .error_o     ( addr_count_err ),
+  .error_cba_o ( /* ... */      )
+);
+
+assign address_o = addr_count [3]; // Result of TMR address voter
+assign fatal_o = addr_count_err; // Error from one of the two TMR voters
+assign done_o = |addr_count_rst;
+
+endmodule : DMR_address_generator