rv_tracer

rv_tracer is developed as part of the PULP project, a joint effort between ETH Zurich and the University of Bologna.

If you find this work useful in your research, please consider citing:

@article{laghi2025efficient,
  title={Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6},
  author={Laghi, Umberto and Manoni, Simone and Parisi, Emanuele and Bartolini, Andrea},
  journal={arXiv preprint arXiv:2504.01972},
  year={2025}
}

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License

Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license. All hardware sources and tool scripts are licensed under the Solderpad Hardware License 0.51 (see LICENSE) or compatible licenses, except for files contained in the img directory, which are licensed under the Creative Commons Attribution-NoDerivates 4.0 International license (CC BY-ND 4.0).
The file generate_do.py is licensed under Apache 2.0 license.

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Short summary

Supported features

Feature	Implemented
Branch Trace
Delta address mode	✅
Full address mode	✅
Implicit exception mode	❌
Sequentially inferable jump mode	❌
Implicit return mode	❌
Branch prediction mode	❌
Jump target cache mode	❌
Instruction Trace Interface
Single-retirement	✅
Multiple-retirement	✅
Trigger unit	✅
Data Trace	❌
Instruction Trace Output Packets
Time	❌
Context	❌

---

Testing progress

Module	Tested
rv_tracer	✅
te_branch_map	✅
te_filter	✅
te_packet_emitter	✅ (no format 0 packets)
te_priority	✅
te_reg	✅
te_resync_counter	✅

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How to run it

After downloading the repo, move inside the repo:

cd rv_tracer

Then run the simulation:

make run

Between one run and the other launch:

make clean

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Design

The modules defined are the following:

• te_reg: stores configuration data, produces clock signal for the other modules;
• te_resync_counter: counts packets emitted or clock cycles and asks for a resynchronization packet;
• te_branch_map: counts the branches and keeps track if they were taken or not;
• te_filter: declares input blocks as "qualified" - they can be processed by the next modules - based on user-defined values read from te_reg;
• te_priority: determines which packet needs to be emitted and performs a simple compression on the address that is put inside the payload;
• te_packet_emitter: populates the payload and can reset both the te_resync_counter and te_branch_map.

Figure 1: high level rv_tracer architecture

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te_reg

This module stores the user and non-user definable parameters.

The user-definable parameters are the following:

• trace_activated
• nocontext
• notime
• encoder_mode
• configuration
• lossless_trace
• shallow_trace
• parameters necessary for the te_filter module

The clock_gated signal depends on the trace_activated signal.

Figure 2: te_reg internal architecture

APB Protocol

To access the registers, an APB interface is required.

Signal Name	Source	Width	Description
PCLK	Clock	1	Clock
PADDR	Requester	ADDR_WIDTH	Address
PSELx	Requester	1	Select
PENABLE	Requester	1	Enable
PWRITE	Requester	1	Direction
PWDATA	Requester	DATA_WIDTH	Write data
PREADY	Completer	1	Ready
PRDATA	Completer	DATA_WIDTH	Read data

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te_branch_map

The te_branch_map module keeps track of branches using a counter and a branch map.

Figure 5: te_branch_map internal architecture

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te_filter

The te_filter filters input blocks to trace specific portions of code.

Figure 6: te_filter internal architecture

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te_priority

Determines which packet needs to be emitted.

Figure 7: flow chart determining packet type

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te_packet_emitter

The te_packet_emitter module populates the payload according to inputs from te_priority.

Figure 11: te_packet_emitter internal architecture

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te_resync_counter

Counts emitted packets or elapsed clock cycles and signals when resynchronization is required.

Figure 12: te_resync_counter internal architecture

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Multiple Retirement Support

Many RISC-V cores can retire up to N instructions per cycle.

Multiple Retirement: Branches Only

Figure 13: rv_tracer architecture for up to N branches in the same cycle

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Multiple Retirement: Not Only Branches

Figure 14: rv_tracer architecture for up to N discontinuities in the same cycle

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Cite this work

If you use rv_tracer in your research, please cite:

@article{laghi2025efficient,
  title={Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6},
  author={Laghi, Umberto and Manoni, Simone and Parisi, Emanuele and Bartolini, Andrea},
  journal={arXiv preprint arXiv:2504.01972},
  year={2025}
}