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There is a
ddr_selsignal in the physical layer, that muxes the high and low bits in DDR mode. Currently, this signal is clocked by the fast system clock, causing a timing path from the fast system clock throughddr_selto the output, which causes timing violations.This PR should fix this by using a (glitch-free) clock mux that selects based on
clk_slowinstead ofddr_sel.ddr_selandclk_slowhave the exact same waveform, butddr_selis treated as a signal by STA, whileclk_slowis a clock. This means the previous violating path is now a clock path, which should not cause any issues anymore in STA.