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renode(TEST-PIX-019): add the M4 third core — M7+M4+F100 co-execute with a LIVE M7↔M4 shared-mem link (Stage 4)#104

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renode/m4-third-core-multinode
Jun 25, 2026
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renode(TEST-PIX-019): add the M4 third core — M7+M4+F100 co-execute with a LIVE M7↔M4 shared-mem link (Stage 4)#104
avrabe merged 1 commit into
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renode/m4-third-core-multinode

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@avrabe avrabe commented Jun 25, 2026

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Extends the Renode multi-node vehicle from M7+F100 to the full three-core 6X-RT topology — the M4 plan (DD-018 T2 sensor-offload core).

New:

  • rt1176-dualcore.replcpu_m7 + cpu_m4 on the shared RT1176 sysbus (per-core NVIC via BusPointRegistration), + a SHMEM ring @ 0x20400000 (relay-bus carrier region, DD-009) + an MU mailbox stub. Kept separate from the CI-gated pixhawk6xrt.repl (M7-only smoke), which is untouched.
  • m4/m4-heartbeat.elf (+ boot.S/link.ld) — a tiny Cortex-M4 firmware (OCRAM vectors/text/stack) that publishes an advancing heartbeat to the SHMEM ring, standing in for the sensor-offload workload until real drivers land.

Confirmed (Renode v1.16.1) — all three cores co-execute:

  • cpu_m7 boots smoke → LPUART1 JESS-RT1176 boot OK
  • cpu_m4 writes ~0xA2C29 to SHMEM @ 0x20400000 after 0.02 s — the on-die M7↔M4 shared-mem link is live (not just instantiated)
  • f100-io (gust) co-executes
  • ORACLE PASS (M7 banner + M4 heartbeat > 0). run-vehicle-multinode.sh updated to the 3-core model with per-core VTOR.

Deferred (status=draft, honest): reactive failsafe handoff needs gust ipc-rx wired to a connectable transport (asked gale#65); real falcon / M4 drivers gated on synth #369/#275; MU doorbell-IRQ is a stub (the ring is live).

rivet validate (v0.18.0): PASS.

🤖 Generated with Claude Code

…ith a LIVE M7<->M4 shared-mem link (Stage 4)

Extends the Renode multi-node vehicle from M7+F100 to the FULL three-core 6X-RT
topology, per the M4 plan (DD-018 T2 sensor-offload core).

NEW: rt1176-dualcore.repl — cpu_m7 + cpu_m4 on the shared RT1176 sysbus (per-core
NVIC via BusPointRegistration), + a SHMEM ring @0x20400000 (relay-bus carrier
region, DD-009) + an MU mailbox stub. Kept SEPARATE from the CI-gated
pixhawk6xrt.repl (M7-only smoke), which is untouched.
NEW: m4/m4-heartbeat.elf (+ boot.S/link.ld) — a tiny Cortex-M4 firmware (OCRAM
vectors/text/stack) that publishes an advancing heartbeat to the SHMEM ring,
standing in for the sensor-offload workload until real drivers land.

CONFIRMED (Renode v1.16.1): all THREE cores co-execute — cpu_m7 -> LPUART1
"JESS-RT1176 boot OK"; cpu_m4 writes ~0xA2C29 to SHMEM @0x20400000 after 0.02s
(the on-die M7<->M4 shared-mem link is LIVE, not just instantiated); f100-io
(gust) co-executes. ORACLE PASS. run-vehicle-multinode.sh updated to the 3-core
model with per-core VTOR (M7=smoke 0x0, M4=heartbeat 0x20240000) + M7-banner and
M4-heartbeat assertions.

DEFERRED (status=draft): reactive failsafe handoff needs gust ipc-rx wired to a
connectable transport (asked gale#65); real falcon/M4-drivers gated on synth
#369/#275; MU doorbell-IRQ is a stub (ring is live).

rivet validate (v0.18.0): PASS.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@avrabe avrabe merged commit d23d150 into main Jun 25, 2026
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@avrabe avrabe deleted the renode/m4-third-core-multinode branch June 25, 2026 03:49
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