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release-watch: falcon-v1.89.0 (CRSF RC decode) per-piece GREEN, gap unchanged (#369 only) #98

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Merged
avrabe merged 1 commit into from
Jun 23, 2026
Merged

release-watch: falcon-v1.89.0 (CRSF RC decode) per-piece GREEN, gap unchanged (#369 only) #98

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4 changes: 4 additions & 0 deletions artifacts/findings.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -792,6 +792,10 @@ artifacts:
is on the synth->ARM ELF, NOT the wasm; witness instruments the wasm core, so this
does NOT change jess's wasm-side stripped-DWARF deviation (still branch-coverage).
Evidence: results/jess-build-falcon-v1.88.0.xml.
UPDATE 2026-06-23 (cron, falcon-v1.89.0 = CRSF RC decode, RC-P03, relay #225):
the RC-input decode series (SBUS v1.88 + CRSF v1.89, both -> bounded RcInput).
Per-piece GREEN on synth v0.12.0, authoritative skips 3/18 all #369 unchanged,
bulk-mem clean - no new unlowerable op. Evidence: results/jess-build-falcon-v1.89.0.xml.
tags: [release-watch, synth, fpu, miscompile, correctness, on-target, blocker]
fields:
detected-by: jess REQ-PIX-001 value-level oracle - silent miscompile resolved in v0.11.46 (GI-FPU-001, verified loud-skip exit 1); OPEN remainder is GI-FPU-002 hard-float
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12 changes: 12 additions & 0 deletions results/jess-build-falcon-v1.89.0.xml
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@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<testsuites>
<testsuite name="jess-build" tests="7" failures="0" skipped="0" errors="0" time="0">
<testcase name="sha256-verify" classname="jess-build" time="0"/>
<testcase name="sil-stabilization" classname="jess-build" time="0"/>
<testcase name="sil-position-hold" classname="jess-build" time="0"/>
<testcase name="meld-fuse" classname="jess-build" time="0"/>
<testcase name="loom-optimize" classname="jess-build" time="0"/>
<testcase name="synth-compile" classname="jess-build" time="0"/>
<testcase name="kiln-xruntime" classname="jess-build" time="0"/>
</testsuite>
</testsuites>
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