chore(release): bump to v0.22.0

Cargo.toml

@@ -27,7 +27,7 @@ members = [
 ]
 
 [workspace.package]
-version = "0.21.0"
+version = "0.22.0"
 edition = "2024"
 license = "MIT"
 repository = "https://github.com/pulseengine/spar"

artifacts/requirements.yaml

@@ -2309,10 +2309,9 @@ artifacts:
       resolves UNAMBIGUOUSLY to a non-bus component, accept otherwise".
       Oracle: a connection bound to a non-bus component warns; one bound to
       a bus, or whose reference cannot be resolved, does not.
-    status: implemented
+    status: verified
+    release: v0.22.0
     tags: [wrpc, binding, analysis]
-    fields:
-      release: v0.22.0
 
   - id: REQ-CODEGEN-WIT-CONN-001
     type: requirement
@@ -3030,10 +3029,9 @@ artifacts:
       GATE: on the converging-bridge fixture the bridge's authoritative bound
       equals TFA (1048 µs) for the cross-burst flow, not the looser PLP.
       [SOLID — Bouillard arXiv:2010.09263]
-    status: implemented
+    status: verified
+    release: v0.22.0
     tags: [network-calculus, plp, bridge, substrate, tier1]
-    fields:
-      release: v0.22.0
 
   - id: REQ-NC-BRIDGE-001
     type: requirement
@@ -3239,10 +3237,9 @@ artifacts:
       synthesize_gcl* family it is library API; no synthesizer is yet wired
       into a CLI / AADL→Qbv consumer, so this REQ makes no end-to-end
       pipeline claim — consumer wiring is separate future work. [SOLID]
-    status: implemented
+    status: verified
+    release: v0.22.0
     tags: [tsn, synthesis, qbv, guard-band, tier2]
-    fields:
-      release: v0.22.0
 
   - id: REQ-TSN-SYNTH-QBV-001
     type: requirement
@@ -3455,6 +3452,20 @@ artifacts:
     type: requirement
     title: "Multi-buffer single-cycle CQF for long links (B-buffer dead-time accommodation)"
     description: >
+      ⚠ SPEC UNDER REVISION — DEFERRED to v0.23.0 (2026-06-27 fresh-context
+      model-pinning). The delay clause below is UNSOUND as written: it
+      conflates the within-cycle dead-time guard band DT (< T_c) with
+      multi-cycle link delay, so when the buffer clause B=ceil(DT/T_c)
+      activates (DT ≥ 3·T_c) the interval INVERTS (e.g. h=1, DT=3·T_c gives
+      D_min=3·T_c > D_max=2·T_c) and goes optimistic exactly in the
+      long-link regime. The SOUND model is per-hop CYCLE-QUANTIZATION:
+      kᵢ=ceil((dᵢ+DT)/T_c); D_max=T_c+Σkᵢ·T_c; D_min=Σ(kᵢ−1)·T_c+DT;
+      buffers key off JITTER Bᵢ=ceil((dᵢᵐᵃˣ−dᵢᵐⁱⁿ)/T_c)+2, B=clamp(maxᵢBᵢ,
+      3,B_cap); csize=T_c·rate unchanged. Degeneracy (all dᵢ<T_c ⇒ kᵢ=1)
+      reproduces the shipped (h+1)·T_c. Build to the corrected model in the
+      v0.23 feature loop (oracle design: degeneracy + 3-hop discrimination
+      + inversion-guard). Original (unsound) text retained below for the
+      rewrite diff:
       spar shall extend the single-cycle CQF synthesizer
       (REQ-TSN-SYNTH-CQF-BASE-001) to use B ∈ [3,7] cyclic buffers so a
       flow's link delay / dead time DT can exceed one cycle without
@@ -3476,9 +3487,8 @@ artifacts:
       Honest non-goal: this is table-stakes long-link support, not the
       heterogeneous-cycle ambition and not the PLP≪TFA NC-tightness wedge.
     status: proposed
+    release: v0.23.0
     tags: [tsn, synthesis, cqf, longlink, detnet]
-    fields:
-      release: v0.22.0
 
   - id: REQ-TSN-EXPORT-YANG-001
     type: requirement

artifacts/verification.yaml

@@ -1943,6 +1943,8 @@ artifacts:
       - type: satisfies
         target: REQ-NC-PLP-MIN-001
 
+      - type: verifies
+        target: REQ-NC-PLP-MIN-001
   - id: TEST-NC-PLP-STR
     type: feature
     title: TFA-strengthened PLP — tightening to EXACT (panco tfa=True oracle)
@@ -2437,6 +2439,8 @@ artifacts:
       - type: satisfies
         target: REQ-TSN-SYNTH-QBV-GUARDBAND-001
 
+      - type: verifies
+        target: REQ-TSN-SYNTH-QBV-GUARDBAND-001
   - id: TEST-TSN-EXPORT-YANG
     type: feature
     title: 802.1Qcw YANG/NETCONF export of a synthesized gate schedule
@@ -3437,6 +3441,8 @@ artifacts:
       - type: satisfies
         target: REQ-WRPC-BINDING-003
 
+      - type: verifies
+        target: REQ-WRPC-BINDING-003
   # ── CI / Verification gate ──────────────────────────────────────────────
 
   - id: TEST-VERIFY-GATE-RUNNER

vscode-spar/package.json

@@ -3,7 +3,7 @@
   "displayName": "AADL (spar)",
   "description": "AADL v2.2/v2.3 language support with live architecture visualization",
   "publisher": "pulseengine",
-  "version": "0.21.0",
+  "version": "0.22.0",
   "license": "MIT",
   "repository": {
     "type": "git",