docs(vcr): log RV32 lever-baseline + scoping slice in the roadmap (#472, #242)

[avrabe]

Traceability sync — frozen-safe

The VCR-* roadmap's update logs had drifted behind the shipped RISC-V lever-port prep (this session's #484 scoping + #485 baselines weren't logged). Records the RV32 lever-baseline slice under VCR-ORACLE-001, its accurate home — it already logs the RV32 oracle slices (the frozen-fixture byte gate and the cmp-select execution differential).

The entry captures:

• the three *_baseline_472 selector tests pinning current pre-lever RV32 codegen at the RiscVOp-stream level (const-address store unfolded, register-form shift, frame-spilled local) — green today, flipping when each lever lands default-on so a codegen change on the un-byte-gated RV32 path surfaces as a reviewed assertion update;
• the scoping finding that reshaped the port: cmp→select is N/A for RV32IMAC (no conditional-move), so it's local-promotion + immediate-shift-fold + a RISC-V-specific const-address-fold, not a 1:1 port.

Frozen-safe

A single description append + a riscv tag on an existing item; no status change, no new links. rivet validate clean — 0 non-cross-repo errors under the CI gate (the 49 ERRORs are all pre-existing cross-repo xrefs to external projects, which the gate filters). The ARM perf levers' roadmap reconciliation is deliberately left to a focused pass rather than slotted into ambiguous homes here.

🤖 Generated with Claude Code

[codecov]

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